2013-11-06 01:12:55 +01:00
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"use strict";
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/**
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* Programmable Interrupt Controller
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* http://stanislavs.org/helppc/8259.html
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*
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* @constructor
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* @param {PIC=} master
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*/
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2014-06-15 22:25:17 +02:00
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function PIC(cpu, master)
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2013-11-06 01:12:55 +01:00
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{
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var
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2014-06-15 22:25:17 +02:00
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io = cpu.io,
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2013-11-06 01:12:55 +01:00
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/**
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* all irqs off
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* @type {number}
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*/
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irq_mask = 0,
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/**
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* @type {number}
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*
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* Bogus default value (both master and slave mapped to 0).
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* Will be initialized by the BIOS
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*/
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irq_map = 0,
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/**
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* in-service register
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* Holds interrupts that are currently being serviced
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* @type {number}
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*/
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isr = 0,
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/**
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* interrupt request register
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* Holds interrupts that have been requested
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* @type {number}
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*/
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irr = 0,
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is_master = master === undefined,
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slave,
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me = this;
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if(is_master)
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{
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2014-06-15 22:25:17 +02:00
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slave = new PIC(cpu, this);
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2013-11-06 01:12:55 +01:00
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2014-06-15 22:25:17 +02:00
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this.check_irqs = function()
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2013-11-06 01:12:55 +01:00
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{
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var enabled_irr = irr & irq_mask;
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if(!enabled_irr)
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{
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2014-06-15 22:25:17 +02:00
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return slave.check_irqs();
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2013-11-06 01:12:55 +01:00
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}
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var irq = enabled_irr & -enabled_irr;
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if(isr && (isr & -isr) <= irq)
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{
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// wait for eoi of higher or same priority interrupt
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return false;
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}
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2014-02-10 23:11:55 +01:00
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var irq_number = Math.int_log2(irq);
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2013-11-25 11:58:36 +01:00
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irq = 1 << irq_number;
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2013-11-06 01:12:55 +01:00
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irr &= ~irq;
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if(irq === 4)
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{
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// this should always return true
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2014-06-15 22:25:17 +02:00
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return slave.check_irqs();
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2013-11-06 01:12:55 +01:00
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}
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2013-11-25 11:58:36 +01:00
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if(!auto_eoi)
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{
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isr |= irq;
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}
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2013-12-28 23:21:43 +01:00
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//dbg_log("master handling irq " + irq_number, LOG_PIC);
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//dbg_trace(LOG_PIC);
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2014-07-26 23:06:52 +02:00
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// call_interrupt_vector can cause an exception in the CPU, so we
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// have to set previous_ip correctly here
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cpu.previous_ip = cpu.instruction_pointer;
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2014-06-15 22:25:17 +02:00
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cpu.call_interrupt_vector(irq_map | irq_number, false, false);
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2013-11-06 01:12:55 +01:00
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return true;
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};
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}
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else
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{
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// is slave
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2014-06-15 22:25:17 +02:00
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this.check_irqs = function()
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2013-11-06 01:12:55 +01:00
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{
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var enabled_irr = irr & irq_mask;
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if(!enabled_irr)
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{
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return false;
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}
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var irq = enabled_irr & -enabled_irr;
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if(isr && (isr & -isr) <= irq)
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{
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// wait for eoi of higher or same priority interrupt
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return false;
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}
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2014-02-10 23:11:55 +01:00
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var irq_number = Math.int_log2(irq);
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2013-11-25 11:58:36 +01:00
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irq = 1 << irq_number;
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2013-11-06 01:12:55 +01:00
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irr &= ~irq;
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isr |= irq;
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2013-12-28 23:21:43 +01:00
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//dbg_log("slave handling irq " + irq_number, LOG_PIC);
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2014-07-26 23:06:52 +02:00
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cpu.previous_ip = cpu.instruction_pointer;
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2014-06-15 22:25:17 +02:00
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cpu.call_interrupt_vector(irq_map | irq_number, false, false);
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2013-11-06 01:12:55 +01:00
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if(irr)
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{
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// tell the master we have one more
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master.push_irq(2);
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}
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2013-11-25 11:58:36 +01:00
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if(!auto_eoi)
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{
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isr &= ~irq;
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}
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2013-11-06 01:12:55 +01:00
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return true;
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};
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}
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this.dump = function()
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{
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dbg_log("mask: " + h(irq_mask & 0xFF), LOG_PIC);
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dbg_log("base: " + h(irq_map), LOG_PIC);
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dbg_log("requested: " + h(irr), LOG_PIC);
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dbg_log("serviced: " + h(isr), LOG_PIC);
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if(is_master)
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{
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slave.dump();
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}
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};
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var expect_icw4,
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state = 0,
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read_irr = 1,
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io_base,
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auto_eoi;
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if(is_master)
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{
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io_base = 0x20;
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}
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else
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{
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io_base = 0xA0;
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}
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io.register_write(io_base, port20_write);
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io.register_read(io_base, port20_read);
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io.register_write(io_base | 1, port21_write);
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io.register_read(io_base | 1, port21_read);
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function port20_write(data_byte)
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{
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//dbg_log("20 write: " + h(data_byte), LOG_PIC);
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if(data_byte & 0x10) // xxxx1xxx
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{
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// icw1
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dbg_log("icw1 = " + h(data_byte), LOG_PIC);
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expect_icw4 = data_byte & 1;
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state = 1;
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}
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else if(data_byte & 8) // xxx01xxx
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{
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// ocw3
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dbg_log("ocw3: " + h(data_byte), LOG_PIC);
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read_irr = data_byte & 1;
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}
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else // xxx00xxx
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{
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// ocw2
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// end of interrupt
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2013-11-25 11:58:36 +01:00
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//dbg_log("eoi: " + h(data_byte), LOG_PIC);
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2013-11-06 01:12:55 +01:00
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var eoi_type = data_byte >> 5;
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if(eoi_type === 1)
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{
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// non-specific eoi
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2013-11-25 11:58:36 +01:00
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isr &= isr - 1;
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2013-11-06 01:12:55 +01:00
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}
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else if(eoi_type === 3)
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{
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// specific eoi
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isr &= ~(1 << (data_byte & 7));
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}
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else
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{
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dbg_log("Unknown eoi: " + h(data_byte), LOG_PIC);
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}
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}
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};
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function port20_read()
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{
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if(read_irr)
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{
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return irr;
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}
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else
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{
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return isr;
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}
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}
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function port21_write(data_byte)
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{
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//dbg_log("21 write: " + h(data_byte), LOG_PIC);
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if(state === 0)
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{
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if(expect_icw4)
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{
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// icw4
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expect_icw4 = false;
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auto_eoi = data_byte & 2;
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dbg_log("icw4: " + h(data_byte), LOG_PIC);
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}
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else
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{
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// ocw1
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irq_mask = ~data_byte;
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2014-07-13 00:42:39 +02:00
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//dbg_log("interrupt mask: " + (irq_mask & 0xFF).toString(2) +
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// " (" + (is_master ? "master" : "slave") + ")", LOG_PIC);
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2013-11-06 01:12:55 +01:00
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}
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}
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else if(state === 1)
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{
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// icw2
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irq_map = data_byte;
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dbg_log("interrupts are mapped to " + h(irq_map) +
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" (" + (is_master ? "master" : "slave") + ")", LOG_PIC);
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state++;
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}
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else if(state === 2)
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{
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// icw3
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state = 0;
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dbg_log("icw3: " + h(data_byte), LOG_PIC);
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}
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};
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function port21_read()
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{
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2013-12-20 22:05:49 +01:00
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//dbg_log("21h read " + h(~irq_mask & 0xff), LOG_PIC);
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return ~irq_mask & 0xFF;
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2013-11-06 01:12:55 +01:00
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};
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if(is_master)
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{
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this.push_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 16);
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if(irq_number >= 8)
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{
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slave.push_irq(irq_number - 8);
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irq_number = 2;
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}
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irr |= 1 << irq_number;
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2014-06-15 22:25:17 +02:00
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cpu.handle_irqs();
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2013-11-06 01:12:55 +01:00
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};
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}
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else
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{
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this.push_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 8);
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irr |= 1 << irq_number;
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};
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}
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this.get_isr = function()
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{
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return isr;
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};
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}
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