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fpu: Have opcode 0xDA use fixed_g instruction functions

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This commit is contained in:
Amaan Cheval 2018-03-21 17:42:50 +05:30 committed by Fabian
parent 41e8a737d5
commit 0f23cf2745
4 changed files with 45 additions and 113 deletions
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2
gen/x86_table.js
View file

@ -163,7 +163,6 @@ const encodings = [
{ opcode: 0xD6, nonfaulting: 1, },
{ opcode: 0xD7, skip: 1, },
{ opcode: 0xDA, e: 1, skip: 1, },
{ opcode: 0xDB, e: 1, skip: 1, },
{ opcode: 0xDC, e: 1, skip: 1, },
{ opcode: 0xDD, e: 1, skip: 1, },
@ -665,6 +664,7 @@ for(let i = 0; i < 8; i++)
{ opcode: 0xD8, e: 1, fixed_g: i, skip: 1, },
{ opcode: 0xD9, e: 1, fixed_g: i, skip: 1, },
{ opcode: 0xDA, e: 1, fixed_g: i, skip: 1, },
]);
}

108
src/native/fpu.c
View file

@ -821,114 +821,6 @@ void fpu_fucompp(void)
fpu_pop();
}
void fpu_op_DA_reg(int32_t imm8)
{
dbg_log_fpu_op(0xDA, imm8);
int32_t mod = imm8 >> 3 & 7;
int32_t low = imm8 & 7;
switch(mod)
{
case 0:
// fcmovb
if(test_b())
{
fpu_st[*fpu_stack_ptr] = fpu_get_sti(low);
*fpu_stack_empty &= ~(1 << *fpu_stack_ptr);
}
break;
case 1:
// fcmove
if(test_z())
{
fpu_st[*fpu_stack_ptr] = fpu_get_sti(low);
*fpu_stack_empty &= ~(1 << *fpu_stack_ptr);
}
break;
case 2:
// fcmovbe
if(test_be())
{
fpu_st[*fpu_stack_ptr] = fpu_get_sti(low);
*fpu_stack_empty &= ~(1 << *fpu_stack_ptr);
}
break;
case 3:
// fcmovu
if(test_p())
{
fpu_st[*fpu_stack_ptr] = fpu_get_sti(low);
*fpu_stack_empty &= ~(1 << *fpu_stack_ptr);
}
break;
case 5:
if(low == 1)
{
// fucompp
fucom(fpu_get_sti(1));
fpu_pop();
fpu_pop();
}
else
{
dbg_log("%x", mod);
fpu_unimpl();
}
break;
default:
dbg_log("%x", mod);
fpu_unimpl();
}
}
void fpu_op_DA_mem(int32_t mod, int32_t addr)
{
dbg_log_fpu_op(0xDA, mod);
int32_t m32 = safe_read32s(addr);
double_t st0 = fpu_get_st0();
switch(mod)
{
case 0:
// fadd
fpu_st[*fpu_stack_ptr] = st0 + m32;
break;
case 1:
// fmul
fpu_st[*fpu_stack_ptr] = st0 * m32;
break;
case 2:
// fcom
fpu_fcom(m32);
break;
case 3:
// fcomp
fpu_fcom(m32);
fpu_pop();
break;
case 4:
// fsub
fpu_st[*fpu_stack_ptr] = st0 - m32;
break;
case 5:
// fsubr
fpu_st[*fpu_stack_ptr] = m32 - st0;
break;
case 6:
// fdiv
fpu_st[*fpu_stack_ptr] = st0 / m32;
break;
case 7:
// fdivr
fpu_st[*fpu_stack_ptr] = m32 / st0;
break;
default:
dbg_assert(false);
}
}
void fpu_op_DB_reg(int32_t imm8)
{
dbg_log_fpu_op(0xDB, imm8);

30
src/native/instructions.c
View file

@ -1152,8 +1152,34 @@ void instr_D9_7_reg(int32_t r) {
fpu_op_D9_7_reg(r);
}
void instr_DA_mem(int32_t addr, int32_t r) { task_switch_test(); fpu_op_DA_mem(r, addr); }
void instr_DA_reg(int32_t r2, int32_t r) { task_switch_test(); fpu_op_DA_reg(0xC0 | r2 | r << 3); }
void instr_DA_0_mem(int32_t addr) { task_switch_test(); fpu_fadd(safe_read32s(addr)); }
void instr_DA_1_mem(int32_t addr) { task_switch_test(); fpu_fmul(safe_read32s(addr)); }
void instr_DA_2_mem(int32_t addr) { task_switch_test(); fpu_fcom(safe_read32s(addr)); }
void instr_DA_3_mem(int32_t addr) { task_switch_test(); fpu_fcomp(safe_read32s(addr)); }
void instr_DA_4_mem(int32_t addr) { task_switch_test(); fpu_fsub(safe_read32s(addr)); }
void instr_DA_5_mem(int32_t addr) { task_switch_test(); fpu_fsubr(safe_read32s(addr)); }
void instr_DA_6_mem(int32_t addr) { task_switch_test(); fpu_fdiv(safe_read32s(addr)); }
void instr_DA_7_mem(int32_t addr) { task_switch_test(); fpu_fdivr(safe_read32s(addr)); }
void instr_DA_0_reg(int32_t r) { task_switch_test(); fpu_fcmovcc(test_b(), r); }
void instr_DA_1_reg(int32_t r) { task_switch_test(); fpu_fcmovcc(test_z(), r); }
void instr_DA_2_reg(int32_t r) { task_switch_test(); fpu_fcmovcc(test_be(), r); }
void instr_DA_3_reg(int32_t r) { task_switch_test(); fpu_fcmovcc(test_p(), r); }
void instr_DA_4_reg(int32_t r) { trigger_ud(); }
void instr_DA_5_reg(int32_t r) {
task_switch_test();
if(r == 1)
{
fpu_fucompp();
}
else
{
trigger_ud();
}
}
void instr_DA_6_reg(int32_t r) { trigger_ud(); }
void instr_DA_7_reg(int32_t r) { trigger_ud(); }
void instr_DB_mem(int32_t addr, int32_t r) { task_switch_test(); fpu_op_DB_mem(r, addr); }
void instr_DB_reg(int32_t r2, int32_t r) { task_switch_test(); fpu_op_DB_reg(0xC0 | r2 | r << 3); }
void instr_DC_mem(int32_t addr, int32_t r) { task_switch_test(); fpu_op_DC_mem(r, addr); }

18
src/native/instructions.h
View file

@ -818,8 +818,22 @@ void instr_D9_6_mem(int32_t addr);
void instr_D9_6_reg(int32_t r);
void instr_D9_7_mem(int32_t addr);
void instr_D9_7_reg(int32_t r);
void instr_DA_mem(int32_t addr, int32_t r);
void instr_DA_reg(int32_t r2, int32_t r);
void instr_DA_0_mem(int32_t addr);
void instr_DA_0_reg(int32_t r);
void instr_DA_1_mem(int32_t addr);
void instr_DA_1_reg(int32_t r);
void instr_DA_2_mem(int32_t addr);
void instr_DA_2_reg(int32_t r);
void instr_DA_3_mem(int32_t addr);
void instr_DA_3_reg(int32_t r);
void instr_DA_4_mem(int32_t addr);
void instr_DA_4_reg(int32_t r);
void instr_DA_5_mem(int32_t addr);
void instr_DA_5_reg(int32_t r);
void instr_DA_6_mem(int32_t addr);
void instr_DA_6_reg(int32_t r);
void instr_DA_7_mem(int32_t addr);
void instr_DA_7_reg(int32_t r);
void instr_DB_mem(int32_t addr, int32_t r);
void instr_DB_reg(int32_t r2, int32_t r);
void instr_DC_mem(int32_t addr, int32_t r);