cpu: Port call_interrupt_vector to Rust
This commit is contained in:
Amaan Cheval
Fabian
parent
48e6843a87
commit
4ef09445e1
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@ -177,9 +177,6 @@ function V86Starter(options)
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return dest;
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},
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"call_interrupt_vector": function(interrupt_nr, is_software_int, has_error_code, error_code) {
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cpu.call_interrupt_vector(interrupt_nr, is_software_int, !!has_error_code, error_code);
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},
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"far_jump": function(eip, selector, is_call) { return cpu.far_jump(eip, selector, !!is_call); },
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"far_return": function(eip, selector, stack_adjust) { return cpu.far_return(eip, selector, stack_adjust); },
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"iret16": function() { return cpu.iret16(); },
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@ -258,6 +255,10 @@ function V86Starter(options)
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"ceil": Math.ceil,
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"fabs": Math.abs,
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"abs": Math.abs,
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"do_task_switch": (selector, error_code) => cpu.do_task_switch(selector, error_code),
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"get_tss_stack_addr": (dpl) => cpu.get_tss_stack_addr(dpl),
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"switch_cs_real_mode": (selector) => cpu.switch_cs_real_mode(selector),
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};
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const wasm_globals = {
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337
src/cpu.js
337
src/cpu.js
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@ -305,6 +305,8 @@ CPU.prototype.wasm_patch = function(wm)
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this.trigger_np = get_import("trigger_np");
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this.trigger_ss = get_import("trigger_ss");
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this.call_interrupt_vector = get_import("call_interrupt_vector");
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this.do_many_cycles_native = get_import("do_many_cycles_native");
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this.cycle_internal = get_import("cycle_internal");
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@ -1452,341 +1454,6 @@ CPU.prototype.jit_clear_cache = function()
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}
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};
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CPU.prototype.call_interrupt_vector = function(interrupt_nr, is_software_int, has_error_code, error_code)
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{
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//dbg_log("int " + h(interrupt_nr, 2) + " (" + (is_software_int ? "soft" : "hard") + "ware)", LOG_CPU);
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CPU_LOG_VERBOSE && this.debug.dump_state("int " + h(interrupt_nr) + " start" +
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" (" + (is_software_int ? "soft" : "hard") + "ware)");
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CPU_LOG_VERBOSE && this.debug.dump_regs();
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this.debug.debug_interrupt(interrupt_nr);
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dbg_assert(typeof has_error_code === "boolean");
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dbg_assert(has_error_code === false || typeof error_code === "number");
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// we have to leave hlt_loop at some point, this is a
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// good place to do it
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//this.in_hlt && dbg_log("Leave HLT loop", LOG_CPU);
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this.in_hlt[0] = +false;
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if(this.protected_mode[0])
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{
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if(this.vm86_mode() && (this.cr[4] & CR4_VME))
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{
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throw this.debug.unimpl("VME");
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}
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if(this.vm86_mode() && is_software_int && this.getiopl() < 3)
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{
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dbg_log("call_interrupt_vector #GP. vm86 && software int && iopl < 3", LOG_CPU);
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dbg_trace(LOG_CPU);
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this.trigger_gp_non_raising(0);
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return;
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}
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if((interrupt_nr << 3 | 7) > this.idtr_size[0])
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{
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dbg_log(interrupt_nr, LOG_CPU);
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dbg_trace(LOG_CPU);
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throw this.debug.unimpl("#GP handler");
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}
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var addr = this.idtr_offset[0] + (interrupt_nr << 3) | 0;
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dbg_assert((addr & 0xFFF) < 0xFF8);
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if(this.cr[0] & CR0_PG)
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{
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addr = this.translate_address_system_read(addr);
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}
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var base = this.read16(addr) | this.read16(addr + 6 | 0) << 16;
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var selector = this.read16(addr + 2 | 0);
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var access = this.read8(addr + 5 | 0);
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var dpl = access >> 5 & 3;
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var type = access & 31;
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if((access & 0x80) === 0)
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{
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// present bit not set
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throw this.debug.unimpl("#NP handler");
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}
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if(is_software_int && dpl < this.cpl[0])
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{
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dbg_log("#gp software interrupt (" + h(interrupt_nr, 2) + ") and dpl < cpl", LOG_CPU);
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dbg_trace(LOG_CPU);
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this.trigger_gp_non_raising(interrupt_nr << 3 | 2);
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return;
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}
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if(type === 5)
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{
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// task gate
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dbg_log("interrupt to task gate: int=" + h(interrupt_nr, 2) + " sel=" + h(selector, 4) + " dpl=" + dpl, LOG_CPU);
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dbg_trace(LOG_CPU);
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this.do_task_switch(selector, error_code);
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CPU_LOG_VERBOSE && this.debug.dump_state("int end");
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return;
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}
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if((type & ~1 & ~8) !== 6)
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{
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// invalid type
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dbg_trace(LOG_CPU);
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dbg_log("invalid type: " + h(type));
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dbg_log(h(addr) + " " + h(base >>> 0) + " " + h(selector));
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throw this.debug.unimpl("#GP handler");
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}
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var is_trap = (type & 1) === 1;
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var is_16 = (type & 8) === 0;
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var info = this.lookup_segment_selector(selector);
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dbg_assert((base >>> 0) <= info.effective_limit);
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dbg_assert(info.is_valid);
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if(info.is_null)
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{
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dbg_log("is null");
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throw this.debug.unimpl("#GP handler");
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}
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if(!info.is_executable || info.dpl > this.cpl[0])
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{
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dbg_log("not exec");
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throw this.debug.unimpl("#GP handler");
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}
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if(!info.is_present)
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{
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// kvm-unit-test
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dbg_log("not present");
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this.trigger_np(interrupt_nr << 3 | 2);
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return;
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}
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var old_flags = this.get_eflags();
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//dbg_log("interrupt " + h(interrupt_nr, 2) + " (" + (is_software_int ? "soft" : "hard") + "ware) from cpl=" + this.cpl[0] + " vm=" + (this.flags[0] & flag_vm) + " cs:eip=" + h(this.sreg[reg_cs], 4) + ":" + h(this.get_real_eip(), 8) + " to cpl="
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if(!info.dc_bit && info.dpl < this.cpl[0])
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{
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// inter privilege level interrupt
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// interrupt from vm86 mode
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//dbg_log("Inter privilege interrupt gate=" + h(selector, 4) + ":" + h(base >>> 0, 8) + " trap=" + is_trap + " 16bit=" + is_16, LOG_CPU);
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//this.debug.dump_regs();
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var tss_stack_addr = this.get_tss_stack_addr(info.dpl);
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if(this.tss_size_32[0])
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{
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var new_esp = this.read32s(tss_stack_addr);
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var new_ss = this.read16(tss_stack_addr + 4 | 0);
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}
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else
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{
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var new_esp = this.read16(tss_stack_addr);
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var new_ss = this.read16(tss_stack_addr + 2 | 0);
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}
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var ss_info = this.lookup_segment_selector(new_ss);
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// Disabled: Incorrect handling of direction bit
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// See http://css.csail.mit.edu/6.858/2014/readings/i386/s06_03.htm
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//if(!((new_esp >>> 0) <= ss_info.effective_limit))
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// debugger;
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//dbg_assert((new_esp >>> 0) <= ss_info.effective_limit);
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dbg_assert(ss_info.is_valid && !ss_info.is_system && ss_info.is_writable);
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if(ss_info.is_null)
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{
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throw this.debug.unimpl("#TS handler");
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}
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if(ss_info.rpl !== info.dpl) // xxx: 0 in v86 mode
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{
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throw this.debug.unimpl("#TS handler");
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}
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if(ss_info.dpl !== info.dpl || !ss_info.rw_bit)
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{
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throw this.debug.unimpl("#TS handler");
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}
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if(!ss_info.is_present)
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{
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throw this.debug.unimpl("#TS handler");
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}
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var old_esp = this.reg32s[reg_esp];
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var old_ss = this.sreg[reg_ss];
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if(old_flags & flag_vm)
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{
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//dbg_log("return from vm86 mode");
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//this.debug.dump_regs();
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dbg_assert(info.dpl === 0, "switch to non-0 dpl from vm86 mode");
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}
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var stack_space = (is_16 ? 2 : 4) * (5 + (has_error_code === true) + 4 * ((old_flags & flag_vm) === flag_vm));
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var new_stack_pointer = ss_info.base + (ss_info.size ? new_esp - stack_space : (new_esp - stack_space & 0xFFFF));
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// XXX: with new cpl or with cpl 0?
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this.translate_address_system_write(new_stack_pointer);
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this.translate_address_system_write(ss_info.base + new_esp - 1);
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// no exceptions below
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this.cpl[0] = info.dpl;
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this.cpl_changed();
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this.update_cs_size(info.size);
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this.flags[0] &= ~flag_vm & ~flag_rf;
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if(!this.switch_seg(reg_ss, new_ss)) dbg_assert(false); // XXX
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this.set_stack_reg(new_esp);
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if(old_flags & flag_vm)
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{
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if(is_16)
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{
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dbg_assert(false);
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}
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else
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{
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this.push32(this.sreg[reg_gs]);
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this.push32(this.sreg[reg_fs]);
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this.push32(this.sreg[reg_ds]);
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this.push32(this.sreg[reg_es]);
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}
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}
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if(is_16)
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{
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this.push16(old_ss);
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this.push16(old_esp);
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}
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else
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{
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this.push32(old_ss);
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this.push32(old_esp);
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}
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}
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else if(info.dc_bit || info.dpl === this.cpl[0])
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{
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// intra privilege level interrupt
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//dbg_log("Intra privilege interrupt gate=" + h(selector, 4) + ":" + h(base >>> 0, 8) +
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// " trap=" + is_trap + " 16bit=" + is_16 +
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// " cpl=" + this.cpl[0] + " dpl=" + info.dpl + " conforming=" + +info.dc_bit, LOG_CPU);
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//this.debug.dump_regs_short();
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if(this.flags[0] & flag_vm)
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{
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dbg_assert(false, "check error code");
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this.trigger_gp_non_raising(selector & ~3);
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return;
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}
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var stack_space = (is_16 ? 2 : 4) * (3 + (has_error_code === true));
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// XXX: with current cpl or with cpl 0?
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if(!this.writable_or_pagefault(this.get_stack_pointer(-stack_space), stack_space))
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{
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return;
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}
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// no exceptions below
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}
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else
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{
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throw this.debug.unimpl("#GP handler");
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}
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if(is_16)
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{
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this.push16(old_flags);
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this.push16(this.sreg[reg_cs]);
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this.push16(this.get_real_eip());
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if(has_error_code === true)
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{
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this.push16(error_code);
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}
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base &= 0xFFFF;
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}
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else
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{
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this.push32(old_flags);
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this.push32(this.sreg[reg_cs]);
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this.push32(this.get_real_eip());
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if(has_error_code === true)
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{
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this.push32(error_code);
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}
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}
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if(old_flags & flag_vm)
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{
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if(
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!this.switch_seg(reg_gs, 0) ||
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!this.switch_seg(reg_fs, 0) ||
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!this.switch_seg(reg_ds, 0) ||
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!this.switch_seg(reg_es, 0)
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)
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{
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// can't fail
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dbg_assert(false);
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}
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}
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this.sreg[reg_cs] = selector & ~3 | this.cpl[0];
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dbg_assert((this.sreg[reg_cs] & 3) === this.cpl[0]);
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this.update_cs_size(info.size);
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this.segment_limits[reg_cs] = info.effective_limit;
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this.segment_offsets[reg_cs] = info.base;
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this.instruction_pointer[0] = this.get_seg(reg_cs) + base | 0;
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this.flags[0] &= ~flag_nt & ~flag_vm & ~flag_rf & ~flag_trap;
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if(!is_trap)
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{
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// clear int flag for interrupt gates
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this.flags[0] &= ~flag_interrupt;
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}
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else
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{
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if((this.flags[0] & flag_interrupt) && !(old_flags & flag_interrupt))
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{
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this.handle_irqs();
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}
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}
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}
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else
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{
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// call 4 byte cs:ip interrupt vector from ivt at cpu.memory 0
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var index = interrupt_nr << 2;
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var new_ip = this.read16(index);
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var new_cs = this.read16(index + 2 | 0);
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// push flags, cs:ip
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this.push16(this.get_eflags());
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this.push16(this.sreg[reg_cs]);
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this.push16(this.get_real_eip());
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this.flags[0] &= ~flag_interrupt;
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this.switch_cs_real_mode(new_cs);
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this.instruction_pointer[0] = this.get_seg(reg_cs) + new_ip | 0;
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}
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//dbg_log("int to:", LOG_CPU);
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CPU_LOG_VERBOSE && this.debug.dump_state("int end");
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};
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CPU.prototype.iret16 = function()
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{
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this.iret(true);
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@ -54,6 +54,5 @@ extern void io_port_write16(int32_t, int32_t);
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extern void io_port_write32(int32_t, int32_t);
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extern int32_t convert_f64_to_i32(double_t);
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extern void jit_clear_func(int32_t index);
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extern void call_interrupt_vector(int32_t interrupt_nr, bool is_software_int, bool has_error_code, int32_t error_code);
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extern void throw_cpu_exception(void);
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extern double_t microtick(void);
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@ -1,11 +1,15 @@
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#![allow(non_upper_case_globals)]
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extern "C" {
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#[no_mangle]
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fn call_interrupt_vector(interrupt: i32, is_software: bool, has_error: bool, error: i32);
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#[no_mangle]
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fn cpu_exception_hook(interrupt: i32) -> bool;
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#[no_mangle]
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fn do_task_switch(selector: i32, error_code: i32);
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#[no_mangle]
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fn get_tss_stack_addr(dpl: u8) -> u32;
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#[no_mangle]
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fn switch_cs_real_mode(selector: i32);
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#[no_mangle]
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fn dbg_trace();
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//#[no_mangle]
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//fn logop(addr: i32, op: i32);
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@ -26,6 +30,7 @@ use cpu2::memory::{
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};
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use cpu2::misc_instr::{
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adjust_stack_reg, get_stack_pointer, getaf, getcf, getof, getpf, getsf, getzf, pop16, pop32s,
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push16, push32,
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};
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use cpu2::modrm::{resolve_modrm16, resolve_modrm32};
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use page::Page;
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@ -339,6 +344,335 @@ impl SegmentDescriptor {
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}
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}
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pub struct InterruptDescriptor {
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raw: u64,
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}
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impl InterruptDescriptor {
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pub fn offset(&self) -> i32 { (self.raw & 0xffff | self.raw >> 32 & 0xffff0000) as i32 }
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pub fn selector(&self) -> u16 { (self.raw >> 16 & 0xffff) as u16 }
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pub fn access_byte(&self) -> u8 { (self.raw >> 40 & 0xff) as u8 }
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pub fn dpl(&self) -> u8 { (self.access_byte() >> 5 & 3) as u8 }
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pub fn gate_type(&self) -> u8 { self.access_byte() & 31 }
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pub fn is_32(&self) -> bool { self.access_byte() & 8 == 8 }
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pub fn is_present(&self) -> bool { self.access_byte() & 0x80 == 0x80 }
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const TASK_GATE: u8 = 0b101;
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const TRAP_GATE: u8 = 0b111;
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}
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#[no_mangle]
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pub unsafe fn call_interrupt_vector(
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interrupt_nr: i32,
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is_software_int: bool,
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has_error_code: bool,
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error_code: i32,
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) {
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// we have to leave hlt_loop at some point, this is a
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// good place to do it
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*in_hlt = false;
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if *protected_mode {
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if vm86_mode() && *cr.offset(4) & CR4_VME != 0 {
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panic!("Unimplemented: VME");
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}
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if vm86_mode() && is_software_int && getiopl() < 3 {
|
||||
dbg_log!("call_interrupt_vector #GP. vm86 && software int && iopl < 3");
|
||||
dbg_trace();
|
||||
trigger_gp_non_raising(0);
|
||||
return;
|
||||
}
|
||||
|
||||
if interrupt_nr << 3 | 7 > *idtr_size {
|
||||
dbg_log!("interrupt_nr={:x} idtr_size={:x}", interrupt_nr, *idtr_size);
|
||||
dbg_trace();
|
||||
panic!("Unimplemented: #GP handler");
|
||||
}
|
||||
|
||||
let descriptor_address = return_on_pagefault!(translate_address_system_read(
|
||||
*idtr_offset + (interrupt_nr << 3)
|
||||
));
|
||||
|
||||
let descriptor = InterruptDescriptor {
|
||||
raw: read64s(descriptor_address) as u64,
|
||||
};
|
||||
|
||||
let mut offset = descriptor.offset();
|
||||
let selector = descriptor.selector() as i32;
|
||||
let dpl = descriptor.dpl();
|
||||
let gate_type = descriptor.gate_type();
|
||||
|
||||
if !descriptor.is_present() {
|
||||
// present bit not set
|
||||
panic!("Unimplemented: #NP handler");
|
||||
}
|
||||
|
||||
if is_software_int && dpl < *cpl {
|
||||
dbg_log!("#gp software interrupt ({:x}) and dpl < cpl", interrupt_nr);
|
||||
dbg_trace();
|
||||
trigger_gp_non_raising(interrupt_nr << 3 | 2);
|
||||
return;
|
||||
}
|
||||
|
||||
if gate_type == InterruptDescriptor::TASK_GATE {
|
||||
// task gate
|
||||
dbg_log!(
|
||||
"interrupt to task gate: int={:x} sel={:x} dpl={}",
|
||||
interrupt_nr,
|
||||
selector,
|
||||
dpl
|
||||
);
|
||||
dbg_trace();
|
||||
|
||||
do_task_switch(selector, error_code);
|
||||
return;
|
||||
}
|
||||
|
||||
if gate_type & !1 & !8 != 6 {
|
||||
// invalid gate_type
|
||||
dbg_trace();
|
||||
dbg_log!("invalid gate_type: 0b{:b}", gate_type);
|
||||
dbg_log!(
|
||||
"addr={:x} offset={:x} selector={:x}",
|
||||
descriptor_address,
|
||||
offset,
|
||||
selector
|
||||
);
|
||||
panic!("Unimplemented: #GP handler");
|
||||
}
|
||||
|
||||
let is_trap = gate_type & 7 == InterruptDescriptor::TRAP_GATE;
|
||||
let is_16 = !descriptor.is_32();
|
||||
|
||||
let cs_segment_descriptor = match return_on_pagefault!(lookup_segment_selector(selector)) {
|
||||
Ok((desc, _)) => desc,
|
||||
Err(selector_unusable) => match selector_unusable {
|
||||
SelectorNullOrInvalid::IsNull => {
|
||||
dbg_log!("is null");
|
||||
panic!("Unimplemented: #GP handler");
|
||||
},
|
||||
SelectorNullOrInvalid::IsInvalid => {
|
||||
dbg_log!("is invalid");
|
||||
panic!("Unimplemented: #GP handler (error code)");
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
dbg_assert!(offset as u32 <= cs_segment_descriptor.effective_limit());
|
||||
|
||||
if !cs_segment_descriptor.is_executable() || cs_segment_descriptor.dpl() > *cpl {
|
||||
dbg_log!("not exec");
|
||||
panic!("Unimplemented: #GP handler");
|
||||
}
|
||||
if !cs_segment_descriptor.is_present() {
|
||||
// kvm-unit-test
|
||||
dbg_log!("not present");
|
||||
trigger_np(interrupt_nr << 3 | 2);
|
||||
return;
|
||||
}
|
||||
|
||||
let old_flags = get_eflags();
|
||||
|
||||
if !cs_segment_descriptor.is_dc() && cs_segment_descriptor.dpl() < *cpl {
|
||||
// inter privilege level interrupt
|
||||
// interrupt from vm86 mode
|
||||
|
||||
if old_flags & FLAG_VM != 0 && cs_segment_descriptor.dpl() == 0 {
|
||||
panic!("Unimplemented: #GP handler for non-0 cs segment dpl when in vm86 mode");
|
||||
}
|
||||
|
||||
let tss_stack_addr = get_tss_stack_addr(cs_segment_descriptor.dpl());
|
||||
|
||||
let new_esp = read32s(tss_stack_addr);
|
||||
let new_ss = read16(tss_stack_addr + if *tss_size_32 { 4 } else { 2 });
|
||||
let (ss_segment_descriptor, ss_segment_selector) =
|
||||
match return_on_pagefault!(lookup_segment_selector(new_ss)) {
|
||||
Ok((desc, sel)) => (desc, sel),
|
||||
Err(_) => {
|
||||
panic!("Unimplemented: #TS handler");
|
||||
},
|
||||
};
|
||||
|
||||
// Disabled: Incorrect handling of direction bit
|
||||
// See http://css.csail.mit.edu/6.858/2014/readings/i386/s06_03.htm
|
||||
//if !((new_esp >>> 0) <= ss_segment_descriptor.effective_limit())
|
||||
// debugger;
|
||||
//dbg_assert!((new_esp >>> 0) <= ss_segment_descriptor.effective_limit());
|
||||
dbg_assert!(!ss_segment_descriptor.is_system() && ss_segment_descriptor.is_writable());
|
||||
|
||||
if ss_segment_selector.rpl() != cs_segment_descriptor.dpl() {
|
||||
panic!("Unimplemented: #TS handler");
|
||||
}
|
||||
if ss_segment_descriptor.dpl() != cs_segment_descriptor.dpl()
|
||||
|| !ss_segment_descriptor.is_rw()
|
||||
{
|
||||
panic!("Unimplemented: #TS handler");
|
||||
}
|
||||
if !ss_segment_descriptor.is_present() {
|
||||
panic!("Unimplemented: #TS handler");
|
||||
}
|
||||
|
||||
let old_esp = *reg32s.offset(ESP as isize);
|
||||
let old_ss = *sreg.offset(SS as isize) as i32;
|
||||
|
||||
let error_code_space = if has_error_code == true { 1 } else { 0 };
|
||||
let vm86_space = if (old_flags & FLAG_VM) == FLAG_VM {
|
||||
1
|
||||
}
|
||||
else {
|
||||
0
|
||||
};
|
||||
let bytes_per_arg = if is_16 { 2 } else { 4 };
|
||||
|
||||
let stack_space = bytes_per_arg * (5 + error_code_space + 4 * vm86_space);
|
||||
let new_stack_pointer = ss_segment_descriptor.base() + if ss_segment_descriptor.is_32()
|
||||
{
|
||||
new_esp - stack_space
|
||||
}
|
||||
else {
|
||||
new_esp - stack_space & 0xFFFF
|
||||
};
|
||||
|
||||
return_on_pagefault!(translate_address_system_write(new_stack_pointer));
|
||||
return_on_pagefault!(translate_address_system_write(
|
||||
ss_segment_descriptor.base() + new_esp - 1
|
||||
));
|
||||
|
||||
*cpl = cs_segment_descriptor.dpl();
|
||||
cpl_changed();
|
||||
|
||||
update_cs_size(cs_segment_descriptor.is_32());
|
||||
|
||||
*flags &= !FLAG_VM & !FLAG_RF;
|
||||
|
||||
if !switch_seg(SS, new_ss) {
|
||||
dbg_assert!(false);
|
||||
} // XXX
|
||||
set_stack_reg(new_esp);
|
||||
|
||||
if old_flags & FLAG_VM != 0 {
|
||||
if is_16 {
|
||||
dbg_assert!(false);
|
||||
}
|
||||
else {
|
||||
push32(*sreg.offset(GS as isize) as i32).unwrap();
|
||||
push32(*sreg.offset(FS as isize) as i32).unwrap();
|
||||
push32(*sreg.offset(DS as isize) as i32).unwrap();
|
||||
push32(*sreg.offset(ES as isize) as i32).unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
if is_16 {
|
||||
push16(old_ss).unwrap();
|
||||
push16(old_esp).unwrap();
|
||||
}
|
||||
else {
|
||||
push32(old_ss).unwrap();
|
||||
push32(old_esp).unwrap();
|
||||
}
|
||||
}
|
||||
else if cs_segment_descriptor.is_dc() || cs_segment_descriptor.dpl() == *cpl {
|
||||
// intra privilege level interrupt
|
||||
|
||||
//dbg_log!("Intra privilege interrupt gate=" + h(selector, 4) + ":" + h(offset >>> 0, 8) +
|
||||
// " trap=" + is_trap + " 16bit=" + is_16 +
|
||||
// " cpl=" + *cpl + " dpl=" + segment_descriptor.dpl() + " conforming=" + +segment_descriptor.dc_bit(), );
|
||||
//debug.dump_regs_short();
|
||||
|
||||
if *flags & FLAG_VM != 0 {
|
||||
dbg_assert!(false, "check error code");
|
||||
trigger_gp_non_raising(selector & !3);
|
||||
return;
|
||||
}
|
||||
|
||||
let bytes_per_arg = if is_16 { 2 } else { 4 };
|
||||
let error_code_space = if has_error_code == true { 1 } else { 0 };
|
||||
|
||||
let stack_space = bytes_per_arg * (3 + error_code_space);
|
||||
|
||||
// XXX: with current cpl or with cpl 0?
|
||||
return_on_pagefault!(writable_or_pagefault(
|
||||
get_stack_pointer(-stack_space),
|
||||
stack_space
|
||||
));
|
||||
|
||||
// no exceptions below
|
||||
}
|
||||
else {
|
||||
panic!("Unimplemented: #GP handler");
|
||||
}
|
||||
|
||||
if is_16 {
|
||||
push16(old_flags).unwrap();
|
||||
push16(*sreg.offset(CS as isize) as i32).unwrap();
|
||||
push16(get_real_eip()).unwrap();
|
||||
|
||||
if has_error_code == true {
|
||||
push16(error_code).unwrap();
|
||||
}
|
||||
|
||||
offset &= 0xFFFF;
|
||||
}
|
||||
else {
|
||||
push32(old_flags).unwrap();
|
||||
push32(*sreg.offset(CS as isize) as i32).unwrap();
|
||||
push32(get_real_eip()).unwrap();
|
||||
|
||||
if has_error_code == true {
|
||||
push32(error_code).unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
if old_flags & FLAG_VM != 0 {
|
||||
if !switch_seg(GS, 0) || !switch_seg(FS, 0) || !switch_seg(DS, 0) || !switch_seg(ES, 0)
|
||||
{
|
||||
// can't fail
|
||||
dbg_assert!(false);
|
||||
}
|
||||
}
|
||||
|
||||
*sreg.offset(CS as isize) = (selector as u16) & !3 | *cpl as u16;
|
||||
dbg_assert!((*sreg.offset(CS as isize) & 3) == *cpl as u16);
|
||||
|
||||
update_cs_size(cs_segment_descriptor.is_32());
|
||||
|
||||
*segment_limits.offset(CS as isize) = cs_segment_descriptor.effective_limit();
|
||||
*segment_offsets.offset(CS as isize) = cs_segment_descriptor.base();
|
||||
|
||||
*instruction_pointer = get_seg(CS) + offset;
|
||||
|
||||
*flags &= !FLAG_NT & !FLAG_VM & !FLAG_RF & !FLAG_TRAP;
|
||||
|
||||
if !is_trap {
|
||||
// clear int flag for interrupt gates
|
||||
*flags &= !FLAG_INTERRUPT;
|
||||
}
|
||||
else {
|
||||
if *flags & FLAG_INTERRUPT != 0 && old_flags & FLAG_INTERRUPT == 0 {
|
||||
handle_irqs();
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
// call 4 byte cs:ip interrupt vector from ivt at cpu.memory 0
|
||||
|
||||
let index = (interrupt_nr << 2) as u32;
|
||||
let new_ip = read16(index);
|
||||
let new_cs = read16(index + 2);
|
||||
|
||||
// push flags, cs:ip
|
||||
push16(get_eflags()).unwrap();
|
||||
push16(*sreg.offset(CS as isize) as i32).unwrap();
|
||||
push16(get_real_eip()).unwrap();
|
||||
|
||||
*flags &= !FLAG_INTERRUPT;
|
||||
|
||||
switch_cs_real_mode(new_cs);
|
||||
*instruction_pointer = get_seg(CS) + new_ip;
|
||||
}
|
||||
}
|
||||
|
||||
//pub fn call_indirect1(f: fn(u16), x: u16) { f(x); }
|
||||
|
||||
pub unsafe fn after_block_boundary() { jit_block_boundary = true; }
|
||||
|
|
|
|||
|
|
@ -17,8 +17,6 @@ extern "C" {
|
|||
#[no_mangle]
|
||||
fn far_return(eip: i32, selector: i32, stack_adjust: i32);
|
||||
#[no_mangle]
|
||||
fn call_interrupt_vector(interrupt: i32, is_software: bool, has_error: bool, error: i32);
|
||||
#[no_mangle]
|
||||
fn iret16();
|
||||
#[no_mangle]
|
||||
fn iret32();
|
||||
|
|
|
|||
Loading…
Reference in a new issue