test mov reg, sreg manually

gen/x86_table.js

@@ -185,7 +185,7 @@ const encodings = [
     { opcode: 0x8A, custom: 1, e: 1, },
     { opcode: 0x8B, custom: 1, os: 1, e: 1, },
 
-    { opcode: 0x8C, os: 1, e: 1, custom: 1 }, // mov reg, sreg
+    { opcode: 0x8C, os: 1, e: 1, custom: 1, skip: 1 }, // mov reg, sreg
     { opcode: 0x8D, reg_ud: 1, os: 1, e: 1, custom_modrm_resolve: 1, custom: 1, }, // lea
     { opcode: 0x8E, block_boundary: 1, e: 1, skip: 1, }, // mov sreg
     { opcode: 0x8F, os: 1, e: 1, fixed_g: 0, custom_modrm_resolve: 1, custom: 1, block_boundary: 1, }, // pop r/m

tests/nasm/mov_sreg.asm

@@ -12,10 +12,21 @@ mydword:
     mov eax, ss
     and eax, 0xffff0000
 
+    mov ebx, -1
+    db 66h
+    mov ebx, ss
+    and ebx, 0xffff0000
+
     ; 32-bit memory move should preserver higher bits
     mov dword [mydword], 0xdeadbeef
     mov [mydword], ss
-    mov ebx, [mydword]
-    and ebx, 0xffff0000
+    mov ecx, [mydword]
+    and ecx, 0xffff0000
+
+    mov dword [mydword+4], 0xdeadbeef
+    db 66h
+    mov [mydword+4], ss
+    mov edx, [mydword+4]
+    and edx, 0xffff0000
 
 %include "footer.inc"

tests/nasm/mov_sreg_ud1.asm

@@ -0,0 +1,8 @@
+global _start
+
+%include "header.inc"
+
+    db 8eh
+    db 3fh
+
+%include "footer.inc"

tests/nasm/mov_sreg_ud2.asm

@@ -0,0 +1,8 @@
+global _start
+
+%include "header.inc"
+
+    db 8ch
+    db 3fh
+
+%include "footer.inc"