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Refactor more

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This commit is contained in:
Fabian 2020-12-31 19:14:31 -06:00
parent 0dd6740526
commit 6ff18e0b80
3 changed files with 18 additions and 23 deletions
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8
src/rust/cpu.rs
View file

@ -1,7 +1,5 @@
// TODO: Make this an instance, so we can plug in a fake cpu
use cpu2;
use page::Page;
use state_flags::CachedStateFlags;
mod unsafe_cpu {
@ -18,12 +16,6 @@ mod unsafe_cpu {
}
}
pub fn tlb_set_has_code(physical_page: Page, has_code: bool) {
unsafe { cpu2::cpu::tlb_set_has_code(physical_page, has_code) }
}
pub fn check_tlb_invariants() { unsafe { cpu2::cpu::check_tlb_invariants() } }
pub fn codegen_finalize(
wasm_table_index: u16,
phys_addr: u32,

22
src/rust/cpu2/cpu.rs
View file

@ -1867,16 +1867,18 @@ pub unsafe fn translate_address_write_jit(address: i32) -> OrPageFault<u32> {
}
#[no_mangle]
pub unsafe fn tlb_set_has_code(physical_page: Page, has_code: bool) {
pub fn tlb_set_has_code(physical_page: Page, has_code: bool) {
let physical_page = physical_page.to_u32();
for i in 0..valid_tlb_entries_count {
let page = valid_tlb_entries[i as usize];
let entry = *tlb_data.offset(page as isize);
for i in 0..unsafe { valid_tlb_entries_count } {
let page = unsafe { valid_tlb_entries[i as usize] };
let entry = unsafe { *tlb_data.offset(page as isize) };
if 0 != entry {
let tlb_physical_page = entry as u32 >> 12 ^ page as u32;
if physical_page == tlb_physical_page {
*tlb_data.offset(page as isize) =
if has_code { entry | TLB_HAS_CODE } else { entry & !TLB_HAS_CODE }
unsafe {
*tlb_data.offset(page as isize) =
if has_code { entry | TLB_HAS_CODE } else { entry & !TLB_HAS_CODE }
}
}
}
}
@ -1884,14 +1886,14 @@ pub unsafe fn tlb_set_has_code(physical_page: Page, has_code: bool) {
}
#[no_mangle]
pub unsafe fn check_tlb_invariants() {
pub fn check_tlb_invariants() {
if !CHECK_TLB_INVARIANTS {
return;
}
for i in 0..valid_tlb_entries_count {
let page = valid_tlb_entries[i as usize];
let entry = *tlb_data.offset(page as isize);
for i in 0..unsafe { valid_tlb_entries_count } {
let page = unsafe { valid_tlb_entries[i as usize] };
let entry = unsafe { *tlb_data.offset(page as isize) };
if 0 == entry || 0 != entry & TLB_IN_MAPPED_RANGE {
// there's no code in mapped memory

11
src/rust/jit.rs
View file

@ -6,6 +6,7 @@ use std::ptr::NonNull;
use analysis::AnalysisType;
use codegen;
use cpu;
use cpu2;
use cpu2::memory;
use cpu_context::CpuContext;
use global_pointers;
@ -517,7 +518,7 @@ pub fn record_entry_point(phys_address: u32) {
.insert(offset_in_page);
if is_new {
cpu::tlb_set_has_code(page, true);
cpu2::cpu::tlb_set_has_code(page, true);
}
}
@ -985,10 +986,10 @@ fn jit_analyze_and_generate(
dbg_assert!(entry_point_count > 0);
cpu::tlb_set_has_code(page, true);
cpu2::cpu::tlb_set_has_code(page, true);
jit_cache_array::check_invariants();
cpu::check_tlb_invariants();
cpu2::cpu::check_tlb_invariants();
let end_addr = 0;
let first_opcode = 0;
@ -1455,7 +1456,7 @@ fn remove_jit_cache_wasm_index(ctx: &mut JitState, page: Page, wasm_table_index:
}
if !jit_page_has_code(page) {
cpu::tlb_set_has_code(page, false);
cpu2::cpu::tlb_set_has_code(page, false);
}
if CHECK_JIT_CACHE_ARRAY_INVARIANTS {
@ -1539,7 +1540,7 @@ pub fn jit_dirty_page(ctx: &mut JitState, page: Page) {
}
if did_have_code {
cpu::tlb_set_has_code(page, false);
cpu2::cpu::tlb_set_has_code(page, false);
}
}