c2rust cleanup (remove wrapping_*)

src/rust/cpu/arith.rs

@@ -136,7 +136,7 @@ pub unsafe fn imul8(source_operand: i32) {
 }
 #[no_mangle]
 pub unsafe fn mul16(source_operand: u32) {
-    let result = source_operand.wrapping_mul(read_reg16(AX) as u32);
+    let result = source_operand * read_reg16(AX) as u32;
     let high_result = result >> 16;
     write_reg16(AX, result as i32);
     write_reg16(DX, high_result as i32);
@@ -184,7 +184,7 @@ pub unsafe fn imul_reg16(mut operand1: i32, mut operand2: i32) -> i32 {
 #[no_mangle]
 pub unsafe fn mul32(source_operand: i32) {
     let dest_operand = read_reg32(EAX);
-    let result = (dest_operand as u32 as u64).wrapping_mul(source_operand as u32 as u64);
+    let result = (dest_operand as u32 as u64) * (source_operand as u32 as u64);
     let result_low = result as i32;
     let result_high = (result >> 32) as i32;
     write_reg32(EAX, result_low);
@@ -621,16 +621,13 @@ pub unsafe fn div8(source_operand: u32) {
     }
     else {
         let target_operand = read_reg16(AX);
-        let result = (target_operand as u32).wrapping_div(source_operand) as u16;
+        let result = (target_operand as u32 / source_operand) as u16;
         if result as i32 >= 256 {
             trigger_de();
         }
         else {
             write_reg8(AL, result as i32);
-            write_reg8(
-                AH,
-                (target_operand as u32).wrapping_rem(source_operand) as i32,
-            );
+            write_reg8(AH, (target_operand as u32 % source_operand) as i32);
         }
         return;
     };
@@ -662,12 +659,12 @@ pub unsafe fn div16_without_fault(source_operand: u32) -> bool {
         return false;
     }
     let target_operand = (read_reg16(AX) | read_reg16(DX) << 16) as u32;
-    let result = target_operand.wrapping_div(source_operand);
+    let result = target_operand / source_operand;
     if result >= 0x10000 {
         return false;
     }
     write_reg16(AX, result as i32);
-    write_reg16(DX, target_operand.wrapping_rem(source_operand) as i32);
+    write_reg16(DX, (target_operand % source_operand) as i32);
     return true;
 }
 pub unsafe fn div16(source_operand: u32) {
@@ -703,11 +700,11 @@ pub unsafe fn div32_without_fault(source_operand: u32) -> bool {
     let target_low = read_reg32(EAX) as u32;
     let target_high = read_reg32(EDX) as u32;
     let target_operand = (target_high as u64) << 32 | target_low as u64;
-    let result = target_operand.wrapping_div(source_operand as u64);
+    let result = target_operand / (source_operand as u64);
     if result > 0xFFFFFFFF {
         return false;
     }
-    let mod_0 = target_operand.wrapping_rem(source_operand as u64) as i32;
+    let mod_0 = (target_operand % source_operand as u64) as i32;
     write_reg32(EAX, result as i32);
     write_reg32(EDX, mod_0);
     return true;

src/rust/cpu/instructions_0f.rs

@@ -2829,7 +2829,7 @@ pub unsafe fn instr_660F73_3_reg(r: i32, imm8: i32) {
         result.u64[1] = destination.u64[1] >> shift
     }
     else if shift <= 127 {
-        result.u64[0] = destination.u64[1] >> shift.wrapping_sub(64);
+        result.u64[0] = destination.u64[1] >> (shift - 64);
         result.u64[1] = 0
     }
     write_xmm_reg128(r, result);
@@ -2854,7 +2854,7 @@ pub unsafe fn instr_660F73_7_reg(r: i32, imm8: i32) {
     }
     else if shift <= 127 {
         result.u64[0] = 0;
-        result.u64[1] = destination.u64[0] << shift.wrapping_sub(64)
+        result.u64[1] = destination.u64[0] << (shift - 64)
     }
     write_xmm_reg128(r, result);
 }
@@ -4827,10 +4827,7 @@ pub unsafe fn instr_660FF3_mem(addr: i32, r: i32) {
 pub unsafe fn instr_0FF4(source: u64, r: i32) {
     // pmuludq mm, mm/m64
     let destination = read_mmx64s(r);
-    write_mmx_reg64(
-        r,
-        (source as u32 as u64).wrapping_mul(destination as u32 as u64),
-    );
+    write_mmx_reg64(r, (source as u32 as u64) * (destination as u32 as u64));
     transition_fpu_to_mmx();
 }
 pub unsafe fn instr_0FF4_reg(r1: i32, r2: i32) { instr_0FF4(read_mmx64s(r1), r2); }
@@ -5058,10 +5055,10 @@ pub unsafe fn instr_660FFA(source: reg128, r: i32) {
     let destination = read_xmm128s(r);
     write_xmm128(
         r,
-        destination.u32[0].wrapping_sub(source.u32[0]) as i32,
-        destination.u32[1].wrapping_sub(source.u32[1]) as i32,
-        destination.u32[2].wrapping_sub(source.u32[2]) as i32,
-        destination.u32[3].wrapping_sub(source.u32[3]) as i32,
+        destination.i32[0] - source.i32[0],
+        destination.i32[1] - source.i32[1],
+        destination.i32[2] - source.i32[2],
+        destination.i32[3] - source.i32[3],
     );
 }
 pub unsafe fn instr_660FFA_reg(r1: i32, r2: i32) { instr_660FFA(read_xmm128s(r1), r2); }
@@ -5071,7 +5068,7 @@ pub unsafe fn instr_660FFA_mem(addr: i32, r: i32) {
 #[no_mangle]
 pub unsafe fn instr_0FFB(source: u64, r: i32) {
     // psubq mm, mm/m64
-    write_mmx_reg64(r, read_mmx64s(r).wrapping_sub(source));
+    write_mmx_reg64(r, read_mmx64s(r) - source);
     transition_fpu_to_mmx();
 }
 pub unsafe fn instr_0FFB_reg(r1: i32, r2: i32) { instr_0FFB(read_mmx64s(r1), r2); }
@@ -5083,8 +5080,8 @@ pub unsafe fn instr_660FFB(source: reg128, r: i32) {
     // psubq xmm, xmm/m128
     // XXX: Aligned access or #gp
     let mut destination = read_xmm128s(r);
-    destination.u64[0] = destination.u64[0].wrapping_sub(source.u64[0]);
-    destination.u64[1] = destination.u64[1].wrapping_sub(source.u64[1]);
+    destination.u64[0] = destination.u64[0] - source.u64[0];
+    destination.u64[1] = destination.u64[1] - source.u64[1];
     write_xmm_reg128(r, destination);
 }
 pub unsafe fn instr_660FFB_reg(r1: i32, r2: i32) { instr_660FFB(read_xmm128s(r1), r2); }
@@ -5174,10 +5171,10 @@ pub unsafe fn instr_660FFE(source: reg128, r: i32) {
     // paddd xmm, xmm/m128
     // XXX: Aligned access or #gp
     let destination = read_xmm128s(r);
-    let dword0 = destination.u32[0].wrapping_add(source.u32[0]) as i32;
-    let dword1 = destination.u32[1].wrapping_add(source.u32[1]) as i32;
-    let dword2 = destination.u32[2].wrapping_add(source.u32[2]) as i32;
-    let dword3 = destination.u32[3].wrapping_add(source.u32[3]) as i32;
+    let dword0 = destination.i32[0] + source.i32[0];
+    let dword1 = destination.i32[1] + source.i32[1];
+    let dword2 = destination.i32[2] + source.i32[2];
+    let dword3 = destination.i32[3] + source.i32[3];
     write_xmm128(r, dword0, dword1, dword2, dword3);
 }
 pub unsafe fn instr_660FFE_reg(r1: i32, r2: i32) { instr_660FFE(read_xmm128s(r1), r2); }

src/rust/cpu/memory.rs

@@ -192,7 +192,7 @@ pub unsafe fn write16(addr: u32, value: i32) {
         mmap_write16(addr, value & 0xFFFF);
     }
     else {
-        ::jit::jit_dirty_cache_small(addr, addr.wrapping_add(2 as u32));
+        ::jit::jit_dirty_cache_small(addr, addr + 2);
         write16_no_mmap_or_dirty_check(addr, value);
     };
 }
@@ -206,7 +206,7 @@ pub unsafe fn write32(addr: u32, value: i32) {
         mmap_write32(addr, value);
     }
     else {
-        ::jit::jit_dirty_cache_small(addr, addr.wrapping_add(4 as u32));
+        ::jit::jit_dirty_cache_small(addr, addr + 4);
         write32_no_mmap_or_dirty_check(addr, value);
     };
 }

src/rust/cpu/misc_instr.rs

@@ -372,7 +372,7 @@ pub unsafe fn fxrstor(addr: i32) {
 
     set_control_word(safe_read16(addr + 0).unwrap() as u16);
     fpu_set_status_word(safe_read16(addr + 2).unwrap() as u16);
-    *fpu_stack_empty = !safe_read8(addr.wrapping_add(4) as i32).unwrap() as u8;
+    *fpu_stack_empty = !safe_read8(addr + 4).unwrap() as u8;
     *fpu_opcode = safe_read16(addr + 6).unwrap();
     *fpu_ip = safe_read32s(addr + 8).unwrap();
     *fpu_ip_selector = safe_read16(addr + 12).unwrap();