ethonion10/v86
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Enabling some stuff in the BIOS

Browse source
This commit is contained in:
copy 2013-12-20 22:12:28 +01:00
parent d7d8c2d2ff
commit 765fc7f06e
4 changed files with 58 additions and 88 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
bios/seabios-config
View file

@ -1,19 +1,23 @@
#
# Automatically generated make config: don't edit
# Automatically generated file; DO NOT EDIT.
# SeaBIOS Configuration
# Sun Nov 18 21:22:50 2012
#
#
# General Features
#
# CONFIG_COREBOOT is not set
CONFIG_QEMU=y
# CONFIG_CSM is not set
CONFIG_QEMU_HARDWARE=y
CONFIG_XEN=y
CONFIG_THREADS=y
# CONFIG_THREAD_OPTIONROMS is not set
CONFIG_RELOCATE_INIT=y
# CONFIG_BOOTMENU is not set
# CONFIG_BOOTORDER is not set
CONFIG_ENTRY_EXTRASTACK=y
CONFIG_MALLOC_UPPERMEMORY=y
#
# Hardware support
@ -26,12 +30,14 @@ CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_SCSI=y
CONFIG_ESP_SCSI=y
CONFIG_LSI_SCSI=y
CONFIG_MEGASAS=y
CONFIG_FLOPPY=y
CONFIG_PS2PORT=y
CONFIG_USB=y
CONFIG_USB_UHCI=y
CONFIG_USB_OHCI=y
CONFIG_USB_EHCI=y
CONFIG_USB_XHCI=y
CONFIG_USB_MSC=y
CONFIG_USB_UAS=y
CONFIG_USB_HUB=y
@ -41,6 +47,7 @@ CONFIG_SERIAL=y
CONFIG_LPT=y
CONFIG_USE_SMM=y
CONFIG_MTRR_INIT=y
# CONFIG_PMTIMER is not set
#
# BIOS interfaces
@ -48,9 +55,9 @@ CONFIG_MTRR_INIT=y
CONFIG_DRIVES=y
CONFIG_CDROM_BOOT=y
CONFIG_CDROM_EMU=y
CONFIG_PCIBIOS=n
CONFIG_APMBIOS=n
CONFIG_PNPBIOS=n
CONFIG_PCIBIOS=y
CONFIG_APMBIOS=y
CONFIG_PNPBIOS=y
CONFIG_OPTIONROMS=y
CONFIG_OPTIONROMS_DEPLOYED=y
CONFIG_PMM=y
@ -61,34 +68,36 @@ CONFIG_MOUSE=y
CONFIG_S3_RESUME=y
CONFIG_VGAHOOKS=y
# CONFIG_DISABLE_A20 is not set
# CONFIG_WRITABLE_UPPERMEMORY is not set
#
# BIOS Tables
#
CONFIG_PIRTABLE=n
CONFIG_MPTABLE=n
CONFIG_SMBIOS=n
CONFIG_ACPI=n
# CONFIG_PIRTABLE is not set
# CONFIG_MPTABLE is not set
# CONFIG_SMBIOS is not set
CONFIG_ACPI=y
CONFIG_ACPI_DSDT=y
#
# VGA ROM
#
# CONFIG_NO_VGABIOS is not set
CONFIG_VGA_STANDARD_VGA=y
# CONFIG_VGA_STANDARD_VGA is not set
# CONFIG_VGA_CIRRUS is not set
# CONFIG_VGA_BOCHS is not set
CONFIG_VGA_BOCHS=y
# CONFIG_VGA_GEODEGX2 is not set
# CONFIG_VGA_GEODELX is not set
CONFIG_BUILD_VGABIOS=y
CONFIG_VGA_VBE=y
CONFIG_VGA_PCI=y
# CONFIG_OVERRIDE_PCI_ID is not set
CONFIG_VGA_VID=0x0000
CONFIG_VGA_DID=0x0000
CONFIG_VGA_VID=0x1234
CONFIG_VGA_DID=0x1111
#
# Debugging
#
CONFIG_DEBUG_LEVEL=2
CONFIG_DEBUG_LEVEL=13
# CONFIG_DEBUG_SERIAL is not set
CONFIG_DEBUG_IO=y

BIN
bios/seabios-debug.bin
View file

Binary file not shown.

BIN
bios/seabios.bin
View file

Binary file not shown.

109
src/instructions.macro.js
View file

@ -588,37 +588,23 @@ op2(0x99,
op2(0x9A, {
// callf
if(protected_mode && !vm86_mode)
{
throw unimpl("16 bit callf in protected mode");
}
else
{
var new_ip = read_imm16();
var new_cs = read_imm16();
var new_ip = read_imm16();
var new_cs = read_imm16();
push16(sreg[reg_cs]);
push16(get_real_ip());
push16(sreg[reg_cs]);
push16(get_real_ip());
switch_seg(reg_cs, new_cs);
instruction_pointer = get_seg(reg_cs) + new_ip | 0;
}
switch_seg(reg_cs, new_cs);
instruction_pointer = get_seg(reg_cs) + new_ip | 0;
}, {
if(protected_mode && !vm86_mode)
{
throw unimpl("callf");
}
else
{
var new_ip = read_imm32s();
var new_cs = read_imm16();
var new_ip = read_imm32s();
var new_cs = read_imm16();
push32(sreg[reg_cs]);
push32(get_real_ip());
push32(sreg[reg_cs]);
push32(get_real_ip());
switch_seg(reg_cs, new_cs);
instruction_pointer = get_seg(reg_cs) + new_ip | 0;
}
switch_seg(reg_cs, new_cs);
instruction_pointer = get_seg(reg_cs) + new_ip | 0;
});
op(0x9B, {
@ -809,67 +795,34 @@ op2(0xC9, {
});
op2(0xCA, {
// retf
if(!protected_mode || vm86_mode)
{
var imm16 = read_imm16();
var ip = pop16();
var imm16 = read_imm16();
var ip = pop16();
switch_seg(reg_cs, pop16());
instruction_pointer = get_seg(reg_cs) + ip | 0;
reg16[reg_sp] += imm16;
}
else
{
throw unimpl("16 bit retf in protected mode");
}
switch_seg(reg_cs, pop16());
instruction_pointer = get_seg(reg_cs) + ip | 0;
reg16[reg_sp] += imm16;
}, {
// retf
var imm16 = read_imm16();
var ip = pop32s();
if(!protected_mode || vm86_mode)
{
throw unimpl("32 bit retf in real/vm86 mode");
}
else
{
//dbg_log("retf");
var ip = pop32s();
switch_seg(reg_cs, pop32s() & 0xFFFF);
instruction_pointer = get_seg(reg_cs) + ip | 0;
switch_seg(reg_cs, pop32s() & 0xFFFF);
instruction_pointer = get_seg(reg_cs) + ip | 0;
stack_reg[reg_vsp] += imm16;
}
stack_reg[reg_vsp] += imm16;
});
op2(0xCB, {
// retf
if(protected_mode && !vm86_mode)
{
throw unimpl("16 bit retf in protected mode");
}
else
{
var ip = pop16();
switch_seg(reg_cs, pop16());
instruction_pointer = get_seg(reg_cs) + ip | 0;
}
var ip = pop16();
switch_seg(reg_cs, pop16());
instruction_pointer = get_seg(reg_cs) + ip | 0;
}, {
// retf
if(protected_mode && !vm86_mode)
{
var ip = pop32s();
var ip = pop32s();
switch_seg(reg_cs, pop32s() & 0xFFFF);
instruction_pointer = get_seg(reg_cs) + ip | 0;
}
else
{
var ip = pop32s();
switch_seg(reg_cs, pop32s() & 0xFFFF);
instruction_pointer = get_seg(reg_cs) + ip | 0;
}
switch_seg(reg_cs, pop32s() & 0xFFFF);
instruction_pointer = get_seg(reg_cs) + ip | 0;
});
op(0xCC, {
@ -1731,6 +1684,7 @@ op(0x09, {
undefined_instruction(0x0A);
op(0x0B, {
// UD2
trigger_ud();
});
undefined_instruction(0x0C);
@ -1807,6 +1761,10 @@ opm(0x21, {
// TODO: mov from debug register
dbg_assert(modrm_byte >= 0xC0);
reg32s[modrm_byte & 7] = dreg[modrm_byte >> 3 & 7];
//dbg_log("read dr" + (modrm_byte >> 3 & 7) + ": " + h(reg32[modrm_byte & 7]), LOG_CPU);
});
opm(0x22, {
@ -1875,6 +1833,9 @@ opm(0x23, {
// TODO: mov to debug register
dbg_assert(modrm_byte >= 0xC0);
//dbg_log("write dr" + (modrm_byte >> 3 & 7) + ": " + h(reg32[modrm_byte & 7]), LOG_CPU);
dreg[modrm_byte >> 3 & 7] = reg32s[modrm_byte & 7];
});
undefined_instruction(0x24);