Use dbg_assert over assert

src/rust/analysis.rs

@@ -43,7 +43,7 @@ pub fn analyze_step_handle_segment_prefix(
     cpu: &mut CpuContext,
     analysis: &mut Analysis,
 ) {
-    assert!(segment <= 5);
+    dbg_assert!(segment <= 5);
     cpu.prefixes |= segment + 1;
     analyze_step_handle_prefix(cpu, analysis)
 }

src/rust/codegen.rs

@@ -265,8 +265,8 @@ pub fn gen_safe_write32(ctx: &mut JitContext, local_for_address: u32, local_for_
 
     // Since this function clobbers other variables, we confirm that the caller uses the local
     // variables we expect them to
-    assert!(local_for_address == GEN_LOCAL_SCRATCH0);
-    assert!(local_for_value == GEN_LOCAL_SCRATCH1);
+    dbg_assert!(local_for_address == GEN_LOCAL_SCRATCH0);
+    dbg_assert!(local_for_value == GEN_LOCAL_SCRATCH1);
 
     let builder = &mut ctx.builder;
     //let instruction_body = &mut ctx.builder.instruction_body;
@@ -369,7 +369,7 @@ pub fn gen_clear_prefixes(ctx: &mut JitContext) {
 }
 
 pub fn gen_add_prefix_bits(ctx: &mut JitContext, mask: u32) {
-    assert!(mask < 0x100);
+    dbg_assert!(mask < 0x100);
 
     let instruction_body = &mut ctx.builder.instruction_body;
     wasm_util::push_i32(instruction_body, global_pointers::PREFIXES as i32); // load address of prefixes

src/rust/cpu_context.rs

@@ -12,15 +12,15 @@ pub struct CpuContext {
 
 impl CpuContext {
     pub fn advance8(&mut self) {
-        assert!(self.eip & 0xFFF < 0xFFF);
+        dbg_assert!(self.eip & 0xFFF < 0xFFF);
         self.eip += 1;
     }
     pub fn advance16(&mut self) {
-        assert!(self.eip & 0xFFF < 0xFFE);
+        dbg_assert!(self.eip & 0xFFF < 0xFFE);
         self.eip += 2;
     }
     pub fn advance32(&mut self) {
-        assert!(self.eip & 0xFFF < 0xFFC);
+        dbg_assert!(self.eip & 0xFFF < 0xFFC);
         self.eip += 4;
     }
     #[allow(unused)]
@@ -34,21 +34,21 @@ impl CpuContext {
     }
 
     pub fn read_imm8(&mut self) -> u8 {
-        assert!(self.eip & 0xFFF < 0xFFF);
+        dbg_assert!(self.eip & 0xFFF < 0xFFF);
         let v = cpu::read8(self.eip);
         self.eip += 1;
         v
     }
     pub fn read_imm8s(&mut self) -> i8 { self.read_imm8() as i8 }
     pub fn read_imm16(&mut self) -> u16 {
-        assert!(self.eip & 0xFFF < 0xFFE);
+        dbg_assert!(self.eip & 0xFFF < 0xFFE);
         let v = cpu::read16(self.eip);
         self.eip += 2;
         v
     }
     pub fn read_imm16s(&mut self) -> i16 { self.read_imm16() as i16 }
     pub fn read_imm32(&mut self) -> u32 {
-        assert!(self.eip & 0xFFF < 0xFFC);
+        dbg_assert!(self.eip & 0xFFF < 0xFFC);
         let v = cpu::read32(self.eip);
         self.eip += 4;
         v

src/rust/global_pointers.rs

@@ -9,10 +9,10 @@ pub const TLB_DATA: u32 = 0x400000;
 pub const MEMORY: u32 = 0x800000;
 
 pub fn get_reg16_offset(r: u32) -> u32 {
-    assert!(r < 8);
+    dbg_assert!(r < 8);
     REG + 4 * r
 }
 pub fn get_reg32_offset(r: u32) -> u32 {
-    assert!(r < 8);
+    dbg_assert!(r < 8);
     REG + 4 * r
 }

src/rust/jit.rs

@@ -416,7 +416,7 @@ pub fn jit_find_cache_entry(phys_address: u32, state_flags: CachedStateFlags) ->
             }
 
             if is_near_end_of_page(phys_address) {
-                assert!(entry.start_addr != phys_address);
+                dbg_assert!(entry.start_addr != phys_address);
                 profiler::stat_increment(stat::S_RUN_INTERPRETED_NEAR_END_OF_PAGE);
             }
         }
@@ -424,7 +424,7 @@ pub fn jit_find_cache_entry(phys_address: u32, state_flags: CachedStateFlags) ->
         if !entry.pending && entry.start_addr == phys_address && entry.state_flags == state_flags {
             #[cfg(debug_assertions)]
             {
-                assert!(cpu::read32(entry.start_addr) == entry.opcode)
+                dbg_assert!(cpu::read32(entry.start_addr) == entry.opcode)
             }
             return cached_code {
                 wasm_table_index: entry.wasm_table_index,
@@ -817,7 +817,7 @@ pub fn codegen_finalize_finished(
     _first_opcode: u32,
     _state_flags: CachedStateFlags,
 ) {
-    assert!(wasm_table_index != 0);
+    dbg_assert!(wasm_table_index != 0);
 
     match ctx
         .wasm_table_index_pending_free
@@ -852,7 +852,7 @@ pub fn codegen_finalize_finished(
 
         for entry in jit_cache_array::iter() {
             if entry.wasm_table_index == wasm_table_index {
-                assert!(!entry.pending);
+                dbg_assert!(!entry.pending);
             }
         }
     }
@@ -1241,7 +1241,7 @@ pub fn jit_dirty_page(ctx: &mut JitState, page: Page) {
             let entry = jit_cache_array::get_mut(cache_array_index);
             let wasm_table_index = entry.wasm_table_index;
 
-            assert!(page == Page::page_of(entry.start_addr));
+            dbg_assert!(page == Page::page_of(entry.start_addr));
 
             let next_cache_array_index = entry.next_index_same_page();
 
@@ -1291,7 +1291,7 @@ pub fn jit_dirty_page(ctx: &mut JitState, page: Page) {
 }
 
 pub fn jit_dirty_cache(ctx: &mut JitState, start_addr: u32, end_addr: u32) {
-    assert!(start_addr < end_addr);
+    dbg_assert!(start_addr < end_addr);
 
     let start_page = Page::page_of(start_addr);
     let end_page = Page::page_of(end_addr - 1);
@@ -1302,7 +1302,7 @@ pub fn jit_dirty_cache(ctx: &mut JitState, start_addr: u32, end_addr: u32) {
 }
 
 pub fn jit_dirty_cache_small(ctx: &mut JitState, start_addr: u32, end_addr: u32) {
-    assert!(start_addr < end_addr);
+    dbg_assert!(start_addr < end_addr);
 
     let start_page = Page::page_of(start_addr);
     let end_page = Page::page_of(end_addr - 1);
@@ -1312,7 +1312,7 @@ pub fn jit_dirty_cache_small(ctx: &mut JitState, start_addr: u32, end_addr: u32)
     // Note: This can't happen when paging is enabled, as writes across
     //       boundaries are split up on two pages
     if start_page != end_page {
-        assert!(start_page.to_u32() + 1 == end_page.to_u32());
+        dbg_assert!(start_page.to_u32() + 1 == end_page.to_u32());
         jit_dirty_page(ctx, end_page);
     }
 }

src/rust/jit_instructions.rs

@@ -33,7 +33,7 @@ pub fn jit_handle_prefix(ctx: &mut JitContext, instr_flags: &mut u32) {
 }
 
 pub fn jit_handle_segment_prefix(segment: u32, ctx: &mut JitContext, instr_flags: &mut u32) {
-    assert!(segment <= 5);
+    dbg_assert!(segment <= 5);
     ctx.cpu.prefixes |= segment + 1;
     // TODO: Could merge multiple prefix updates into one
     codegen::gen_add_prefix_bits(ctx, segment + 1);

src/rust/modrm.rs

@@ -16,7 +16,7 @@ pub fn skip(ctx: &mut CpuContext, modrm_byte: u8) {
 }
 
 fn skip16(ctx: &mut CpuContext, modrm_byte: u8) {
-    assert!(modrm_byte < 0xC0);
+    dbg_assert!(modrm_byte < 0xC0);
     let r = modrm_byte & 7;
 
     if modrm_byte < 0x40 {
@@ -33,7 +33,7 @@ fn skip16(ctx: &mut CpuContext, modrm_byte: u8) {
 }
 
 fn skip32(ctx: &mut CpuContext, modrm_byte: u8) {
-    assert!(modrm_byte < 0xC0);
+    dbg_assert!(modrm_byte < 0xC0);
     let r = modrm_byte & 7;
 
     if r == 4 {