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Add missing sse3 instruction and add note on others

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This commit is contained in:
Fabian 2018-07-26 15:06:50 -06:00
parent bad796b9eb
commit 9f2c78efb4
2 changed files with 15 additions and 11 deletions
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25
gen/x86_table.js
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@ -476,8 +476,8 @@ const encodings = [
{ sse: 1, opcode: 0xF20F11, e: 1 },
{ sse: 1, opcode: 0x0F12, e: 1 },
{ sse: 1, opcode: 0x660F12, only_mem: 1, e: 1 },
{ sse: 1, opcode: 0xF20F12, e: 1, skip: 1, },
{ sse: 1, opcode: 0xF30F12, e: 1, skip: 1, },
{ sse: 1, opcode: 0xF20F12, e: 1, skip: 1, }, // sse3
{ sse: 1, opcode: 0xF30F12, e: 1, skip: 1, }, // sse3
{ sse: 1, opcode: 0x0F13, only_mem: 1, e: 1 },
{ sse: 1, opcode: 0x660F13, only_mem: 1, e: 1 },
{ sse: 1, opcode: 0x0F14, e: 1 },
@ -486,6 +486,7 @@ const encodings = [
{ sse: 1, opcode: 0x660F15, e: 1 },
{ sse: 1, opcode: 0x0F16, e: 1 },
{ sse: 1, opcode: 0x660F16, only_mem: 1, e: 1 },
{ sse: 1, opcode: 0xF30F16, skip: 1, }, // sse3
{ sse: 1, opcode: 0x0F17, only_mem: 1, e: 1 },
{ sse: 1, opcode: 0x660F17, only_mem: 1, e: 1 },
@ -597,12 +598,14 @@ const encodings = [
{ sse: 1, opcode: 0x660F76, e: 1, },
{ sse: 1, opcode: 0x0F77 },
{ sse: 1, opcode: 0x0F78, skip: 1 },
{ sse: 1, opcode: 0x0F79, skip: 1 },
{ sse: 1, opcode: 0x0F7A, skip: 1 },
{ sse: 1, opcode: 0x0F7B, skip: 1 },
{ sse: 1, opcode: 0x0F7C, skip: 1 },
{ sse: 1, opcode: 0x0F7D, skip: 1 },
// vmx instructions
{ opcode: 0x0F78, skip: 1 },
{ opcode: 0x0F79, skip: 1 },
{ opcode: 0x0F7A, skip: 1 }, // ud
{ opcode: 0x0F7B, skip: 1 }, // ud
{ sse: 1, opcode: 0x0F7C, skip: 1 }, // sse3
{ sse: 1, opcode: 0x0F7D, skip: 1 }, // sse3
{ sse: 1, opcode: 0x0F7E, e: 1 },
{ sse: 1, opcode: 0x660F7E, e: 1 },
@ -614,15 +617,15 @@ const encodings = [
{ sse: 1, opcode: 0x0FC2, skip: 1, },
{ opcode: 0x0FC3, e: 1, only_mem: 1, }, // movnti: Uses normal registers, hence not marked as sse
{ sse: 1, opcode: 0x0FC4, e: 1, imm8: 1 },
{ sse: 1, opcode: 0x660FC4, e: 1, imm8: 1 },
{ sse: 1, opcode: 0x0FC5, e: 1, only_reg: 1, imm8: 1 },
{ sse: 1, opcode: 0x660FC5, e: 1, only_reg: 1, imm8: 1, },
{ sse: 1, opcode: 0x0FC6, skip: 1, },
{ sse: 1, opcode: 0x0FD0, skip: 1, },
{ sse: 1, opcode: 0x0FD0, skip: 1, }, // sse3
{ sse: 1, opcode: 0x0FD1, e: 1 },
{ sse: 1, opcode: 0x660FD1, e: 1 },
@ -696,7 +699,7 @@ const encodings = [
{ sse: 1, opcode: 0x0FEF, e: 1 },
{ sse: 1, opcode: 0x660FEF, e: 1 },
{ sse: 1, opcode: 0x0FF0, skip: 1, },
{ sse: 1, opcode: 0x0FF0, skip: 1, }, // sse3
{ sse: 1, opcode: 0x0FF1, e: 1 },
{ sse: 1, opcode: 0x660FF1, e: 1 },

1
src/native/instructions_0f.c
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@ -400,6 +400,7 @@ void instr_660F16_mem(int32_t addr, int32_t r) {
movh_m64_r128(addr, r);
}
void instr_660F16_reg(int32_t r1, int32_t r2) { trigger_ud(); }
void instr_F30F16() { unimplemented_sse(); }
void instr_0F17_mem(int32_t addr, int32_t r) {
// movhps m64, xmm