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reformat msrs

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This commit is contained in:
Fabian 2022-10-17 22:36:39 -05:00
parent 2a8a89dd34
commit d0ca758177
2 changed files with 102 additions and 152 deletions
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33
src/rust/cpu/cpu.rs
View file

@ -189,29 +189,30 @@ pub const TSR_FS: i32 = 0x58;
pub const TSR_GS: i32 = 0x5c;
pub const TSR_LDT: i32 = 0x60;
pub const IA32_SYSENTER_CS: i32 = 372;
pub const IA32_SYSENTER_ESP: i32 = 373;
pub const IA32_SYSENTER_EIP: i32 = 374;
pub const IA32_TIME_STAMP_COUNTER: i32 = 16;
pub const IA32_PLATFORM_ID: i32 = 23;
pub const IA32_APIC_BASE_MSR: i32 = 27;
pub const IA32_TIME_STAMP_COUNTER: i32 = 0x10;
pub const IA32_PLATFORM_ID: i32 = 0x17;
pub const IA32_APIC_BASE: i32 = 0x1B;
pub const MSR_TEST_CTRL: i32 = 0x33;
pub const MSR_SMI_COUNT: i32 = 0x34;
pub const IA32_FEAT_CTL: i32 = 0x3A;
pub const IA32_SPEC_CTRL: i32 = 0x48;
pub const IA32_BIOS_SIGN_ID: i32 = 0x8B;
pub const MSR_PLATFORM_INFO: i32 = 0xCE;
pub const MSR_TSX_FORCE_ABORT: i32 = 0x10F;
pub const IA32_TSX_CTRL: i32 = 0x122;
pub const IA32_MCU_OPT_CTRL: i32 = 0x123;
pub const IA32_BIOS_SIGN_ID: i32 = 139;
pub const MSR_PLATFORM_INFO: i32 = 206;
pub const MSR_MISC_FEATURE_ENABLES: i32 = 320;
pub const IA32_MISC_ENABLE: i32 = 416;
pub const IA32_RTIT_CTL: i32 = 1392;
pub const MSR_SMI_COUNT: i32 = 52;
pub const MSR_TEST_CTRL: i32 = 0x33;
pub const IA32_FEAT_CTL: i32 = 0x3a;
pub const MISC_FEATURE_ENABLES: i32 = 0x140;
pub const IA32_SYSENTER_CS: i32 = 0x174;
pub const IA32_SYSENTER_ESP: i32 = 0x175;
pub const IA32_SYSENTER_EIP: i32 = 0x176;
pub const IA32_MCG_CAP: i32 = 0x179;
pub const IA32_MISC_ENABLE: i32 = 0x1A0;
pub const IA32_PAT: i32 = 0x277;
pub const IA32_MCG_CAP: i32 = 377;
pub const IA32_RTIT_CTL: i32 = 0x570;
pub const MSR_PKG_C2_RESIDENCY: i32 = 0x60D;
pub const IA32_KERNEL_GS_BASE: i32 = 0xC0000101u32 as i32;
pub const MSR_AMD64_LS_CFG: i32 = 0xC0011020u32 as i32;
pub const MSR_PKG_C2_RESIDENCY: i32 = 1549;
pub const IA32_APIC_BASE_BSP: i32 = 1 << 8;
pub const IA32_APIC_BASE_EXTD: i32 = 1 << 10;
pub const IA32_APIC_BASE_EN: i32 = 1 << 11;

221
src/rust/cpu/instructions_0f.rs
View file

@ -1171,71 +1171,47 @@ pub unsafe fn instr_0F30() {
dbg_log!("wrmsr ecx={:x} data={:x}:{:x}", index, high, low);
}
if index == IA32_SYSENTER_CS {
*sysenter_cs = low & 0xFFFF
}
else if index == IA32_SYSENTER_EIP {
*sysenter_eip = low
}
else if index == IA32_SYSENTER_ESP {
*sysenter_esp = low
}
else if index == IA32_FEAT_CTL {
// linux 5.x
}
else if index == MSR_TEST_CTRL {
// linux 5.x
}
else if index == IA32_APIC_BASE_MSR {
dbg_assert!(
high == 0,
("Changing APIC address (high 32 bits) not supported")
);
let address = low & !(IA32_APIC_BASE_BSP | IA32_APIC_BASE_EXTD | IA32_APIC_BASE_EN);
dbg_assert!(
address == APIC_ADDRESS,
("Changing APIC address not supported")
);
dbg_assert!(low & IA32_APIC_BASE_EXTD == 0, "x2apic not supported");
*apic_enabled = low & IA32_APIC_BASE_EN == IA32_APIC_BASE_EN
}
else if index == IA32_TIME_STAMP_COUNTER {
set_tsc(low as u32, high as u32);
}
else if index == IA32_BIOS_SIGN_ID {
//
}
else if index == MSR_MISC_FEATURE_ENABLES {
// Linux 4, see: https://patchwork.kernel.org/patch/9528279/
}
else if index == IA32_MISC_ENABLE {
// Enable Misc. Processor Features
}
else if index == IA32_MCG_CAP {
// netbsd
}
else if index == IA32_KERNEL_GS_BASE {
// Only used in 64 bit mode (by SWAPGS), but set by kvm-unit-test
dbg_log!("GS Base written");
}
else if index == IA32_PAT {
//
}
else if index == IA32_SPEC_CTRL {
// linux 5.19
}
else if index == IA32_TSX_CTRL {
// linux 5.19
}
else if index == MSR_TSX_FORCE_ABORT {
// linux 5.19
}
else if index == IA32_MCU_OPT_CTRL {
// linux 5.19
}
else {
dbg_log!("Unknown msr: {:x}", index);
dbg_assert!(false);
match index {
IA32_SYSENTER_CS => *sysenter_cs = low & 0xFFFF,
IA32_SYSENTER_EIP => *sysenter_eip = low,
IA32_SYSENTER_ESP => *sysenter_esp = low,
IA32_FEAT_CTL => {}, // linux 5.x
MSR_TEST_CTRL => {}, // linux 5.x
IA32_APIC_BASE => {
dbg_assert!(
high == 0,
("Changing APIC address (high 32 bits) not supported")
);
let address = low & !(IA32_APIC_BASE_BSP | IA32_APIC_BASE_EXTD | IA32_APIC_BASE_EN);
dbg_assert!(
address == APIC_ADDRESS,
("Changing APIC address not supported")
);
dbg_assert!(low & IA32_APIC_BASE_EXTD == 0, "x2apic not supported");
*apic_enabled = low & IA32_APIC_BASE_EN == IA32_APIC_BASE_EN
},
IA32_TIME_STAMP_COUNTER => set_tsc(low as u32, high as u32),
IA32_BIOS_SIGN_ID => {},
MISC_FEATURE_ENABLES => {
// Linux 4, see: https://patchwork.kernel.org/patch/9528279/
},
IA32_MISC_ENABLE => {
// Enable Misc. Processor Features
},
IA32_MCG_CAP => {}, // netbsd
IA32_KERNEL_GS_BASE => {
// Only used in 64 bit mode (by SWAPGS), but set by kvm-unit-test
dbg_log!("GS Base written");
},
IA32_PAT => {},
IA32_SPEC_CTRL => {}, // linux 5.19
IA32_TSX_CTRL => {}, // linux 5.19
MSR_TSX_FORCE_ABORT => {}, // linux 5.19
IA32_MCU_OPT_CTRL => {}, // linux 5.19
_ => {
dbg_log!("Unknown msr: {:x}", index);
dbg_assert!(false);
},
}
}
@ -1268,78 +1244,51 @@ pub unsafe fn instr_0F32() {
let mut low: i32 = 0;
let mut high: i32 = 0;
if index == IA32_SYSENTER_CS {
low = *sysenter_cs
}
else if index == IA32_SYSENTER_EIP {
low = *sysenter_eip
}
else if index == IA32_SYSENTER_ESP {
low = *sysenter_esp
}
else if index == IA32_TIME_STAMP_COUNTER {
let tsc = read_tsc();
low = tsc as i32;
high = (tsc >> 32) as i32
}
else if index == IA32_FEAT_CTL {
// linux 5.x
}
else if index == MSR_TEST_CTRL {
// linux 5.x
}
else if index == IA32_PLATFORM_ID {
}
else if index == IA32_APIC_BASE_MSR {
if *acpi_enabled {
low = APIC_ADDRESS;
if *apic_enabled {
low |= IA32_APIC_BASE_EN
match index {
IA32_SYSENTER_CS => low = *sysenter_cs,
IA32_SYSENTER_EIP => low = *sysenter_eip,
IA32_SYSENTER_ESP => low = *sysenter_esp,
IA32_TIME_STAMP_COUNTER => {
let tsc = read_tsc();
low = tsc as i32;
high = (tsc >> 32) as i32
},
IA32_FEAT_CTL => {}, // linux 5.x
MSR_TEST_CTRL => {}, // linux 5.x
IA32_PLATFORM_ID => {},
IA32_APIC_BASE => {
if *acpi_enabled {
low = APIC_ADDRESS;
if *apic_enabled {
low |= IA32_APIC_BASE_EN
}
}
}
}
else if index == IA32_BIOS_SIGN_ID {
}
else if index == MSR_PLATFORM_INFO {
low = 1 << 8
}
else if index == MSR_MISC_FEATURE_ENABLES {
}
else if index == IA32_MISC_ENABLE {
// Enable Misc. Processor Features
low = 1 << 0; // fast string
}
else if index == IA32_RTIT_CTL {
// linux4
}
else if index == MSR_SMI_COUNT {
}
else if index == IA32_MCG_CAP {
// netbsd
}
else if index == IA32_PAT {
//
}
else if index == MSR_PKG_C2_RESIDENCY {
}
else if index == IA32_SPEC_CTRL {
// linux 5.19
}
else if index == IA32_TSX_CTRL {
// linux 5.19
}
else if index == MSR_TSX_FORCE_ABORT {
// linux 5.19
}
else if index == IA32_MCU_OPT_CTRL {
// linux 5.19
}
else if index == MSR_AMD64_LS_CFG {
// linux 5.19
}
else {
dbg_log!("Unknown msr: {:x}", index);
dbg_assert!(false);
},
IA32_BIOS_SIGN_ID => {},
MSR_PLATFORM_INFO => low = 1 << 8,
MISC_FEATURE_ENABLES => {},
IA32_MISC_ENABLE => {
// Enable Misc. Processor Features
low = 1 << 0; // fast string
},
IA32_RTIT_CTL => {
// linux4
},
MSR_SMI_COUNT => {},
IA32_MCG_CAP => {
// netbsd
},
IA32_PAT => {},
MSR_PKG_C2_RESIDENCY => {},
IA32_SPEC_CTRL => {}, // linux 5.19
IA32_TSX_CTRL => {}, // linux 5.19
MSR_TSX_FORCE_ABORT => {}, // linux 5.19
IA32_MCU_OPT_CTRL => {}, // linux 5.19
MSR_AMD64_LS_CFG => {}, // linux 5.19
_ => {
dbg_log!("Unknown msr: {:x}", index);
dbg_assert!(false);
},
}
write_reg32(EAX, low);