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instructions: Call after_block_boundary from interpreter not instr

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The instruction body shouldn't include anything but the instruction's
implementation.
This commit is contained in:
Amaan Cheval 2018-04-03 08:47:29 +05:30 committed by Fabian
parent f0829e5e31
commit dffca42ca7
5 changed files with 10 additions and 22 deletions
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17
gen/generate_interpreter.js
View file

@ -126,6 +126,8 @@ function gen_instruction_body(encodings, size)
console.assert((encoding.opcode & 0xFF00) === 0x0F00);
}
const instruction_postfix = encoding.block_boundary ? ["after_block_boundary();"] : [];
if(encoding.fixed_g !== undefined)
{
// instruction with modrm byte where the middle 3 bits encode the instruction
@ -146,6 +148,7 @@ function gen_instruction_body(encodings, size)
cases: cases.map(case_ => {
const fixed_g = case_.fixed_g;
const instruction_name = make_instruction_name(case_, size, undefined);
const instruction_postfix = case_.block_boundary ? ["after_block_boundary();"] : [];
let modrm_resolve_prefix = undefined;
@ -197,12 +200,12 @@ function gen_instruction_body(encodings, size)
if_blocks,
else_block,
},
],
].concat(instruction_postfix),
};
}
else
{
const body = [gen_modrm_mem_reg_split(instruction_name, modrm_resolve_prefix, mem_args, reg_args)];
const body = [gen_modrm_mem_reg_split(instruction_name, modrm_resolve_prefix, mem_args, reg_args)].concat(instruction_postfix);
return {
conditions: [fixed_g],
@ -218,7 +221,7 @@ function gen_instruction_body(encodings, size)
],
}
}
];
].concat(instruction_postfix);
}
else if(has_66 || has_F2 || has_F3)
{
@ -270,7 +273,7 @@ function gen_instruction_body(encodings, size)
if_blocks,
else_block,
}
];
].concat(instruction_postfix);
}
else if(encoding.fixed_g === undefined && encoding.e)
{
@ -300,7 +303,7 @@ function gen_instruction_body(encodings, size)
return [
"int32_t modrm_byte = read_imm8();",
gen_call(instruction_name, ["modrm_byte & 7", "modrm_byte >> 3 & 7"]),
];
].concat(instruction_postfix);
}
else
{
@ -316,7 +319,7 @@ function gen_instruction_body(encodings, size)
return [
"int32_t modrm_byte = read_imm8();",
gen_modrm_mem_reg_split(instruction_name, modrm_resolve_prefix, mem_args, reg_args),
];
].concat(instruction_postfix);
}
}
else
@ -344,7 +347,7 @@ function gen_instruction_body(encodings, size)
args.push("read_imm8()");
}
return [gen_call(instruction_name, args)];
return [gen_call(instruction_name, args)].concat(instruction_postfix);
}
}

5
src/native/cpu.c
View file

@ -38,11 +38,6 @@ void after_block_boundary()
jit_block_boundary = true;
}
void altered_state()
{
after_block_boundary();
}
void diverged()
{
after_block_boundary();

1
src/native/cpu.h
View file

@ -85,7 +85,6 @@ int32_t valid_tlb_entries_count;
extern void call_indirect(int32_t index);
void after_block_boundary(void);
void altered_state(void);
void diverged(void);
void branch_taken(void);
void branch_not_taken(void);

7
src/native/instructions.c
View file

@ -89,14 +89,12 @@ void instr16_17() {
adjust_stack_reg(2);
//clear_prefixes();
//cycle_internal();
altered_state();
}
void instr32_17() {
switch_seg(SS, safe_read32s(get_stack_pointer(0)) & 0xFFFF);
adjust_stack_reg(4);
//clear_prefixes();
//cycle_internal();
altered_state();
}
DEFINE_MODRM_INSTR_READ_WRITE_8(instr_18, sbb8(___, read_reg8(r)))
@ -115,12 +113,10 @@ void instr32_1E() { push32(sreg[DS]); }
void instr16_1F() {
switch_seg(DS, safe_read16(get_stack_pointer(0)));
adjust_stack_reg(2);
altered_state();
}
void instr32_1F() {
switch_seg(DS, safe_read32s(get_stack_pointer(0)) & 0xFFFF);
adjust_stack_reg(4);
altered_state();
}
DEFINE_MODRM_INSTR_READ_WRITE_8(instr_20, and8(___, read_reg8(r)))
@ -571,7 +567,6 @@ void instr_8E_helper(int32_t data, int32_t mod)
{
dbg_log("mov sreg #ud");
}
altered_state();
}
DEFINE_MODRM_INSTR_READ16(instr_8E, instr_8E_helper(___, r))
@ -904,12 +899,10 @@ void instr32_C4_mem(int32_t addr, int32_t r) {
void instr16_C5_reg(int32_t _unused1, int32_t _unused2) { trigger_ud(); }
void instr16_C5_mem(int32_t addr, int32_t r) {
lss16(addr, get_reg16_index(r), DS);
altered_state();
}
void instr32_C5_reg(int32_t _unused1, int32_t _unused2) { trigger_ud(); }
void instr32_C5_mem(int32_t addr, int32_t r) {
lss32(addr, r, DS);
altered_state();
}
void instr_C6_0_reg(int32_t r, int32_t imm) { write_reg8(r, imm); }

2
src/native/instructions_0f.c
View file

@ -2241,12 +2241,10 @@ void instr32_0FB1_mem(int32_t addr, int32_t r) {
void instr16_0FB2_reg(int32_t unused, int32_t unused2) { trigger_ud(); }
void instr16_0FB2_mem(int32_t addr, int32_t r) {
lss16(addr, get_reg16_index(r), SS);
altered_state();
}
void instr32_0FB2_reg(int32_t unused, int32_t unused2) { trigger_ud(); }
void instr32_0FB2_mem(int32_t addr, int32_t r) {
lss32(addr, r, SS);
altered_state();
}
void instr16_0FB3_reg(int32_t r1, int32_t r2) { write_reg16(r1, btr_reg(read_reg16(r1), read_reg16(r2) & 15)); }