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Codegen for fpu instructions (misc instructions) (D9_[14], DB_5, DD_5, DF_4)

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Fabian 2018-12-06 12:32:19 -06:00
parent 1eab44746b
commit ec846b34d9
2 changed files with 60 additions and 5 deletions
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11
gen/x86_table.js
View file

@ -283,10 +283,10 @@ const encodings = [
{ opcode: 0xD8, e: 1, fixed_g: 7, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xD9, e: 1, fixed_g: 0, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xD9, e: 1, fixed_g: 1, custom: 0, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xD9, e: 1, fixed_g: 1, custom: 1, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // skipped: #ud not supported by nasmtests in compiled code
{ opcode: 0xD9, e: 1, fixed_g: 2, custom: 1, is_fpu: 1, task_switch_test: 1, only_mem: 1 }, // skipped: #ud not supported by nasmtests in compiled code
{ opcode: 0xD9, e: 1, fixed_g: 3, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xD9, e: 1, fixed_g: 4, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // fldenv
{ opcode: 0xD9, e: 1, fixed_g: 4, custom: 1, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // fldenv
{ opcode: 0xD9, e: 1, fixed_g: 5, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xD9, e: 1, fixed_g: 6, custom: 0, is_fpu: 1, task_switch_test: 1, skip: 1, }, // fstenv (mem), fprem (reg)
{ opcode: 0xD9, e: 1, fixed_g: 7, custom: 1, is_fpu: 1, task_switch_test: 1, only_mem: 1, }, // fprem
@ -305,7 +305,7 @@ const encodings = [
{ opcode: 0xDB, e: 1, fixed_g: 2, custom: 2, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDB, e: 1, fixed_g: 3, custom: 2, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDB, e: 1, fixed_g: 4, custom: 0, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDB, e: 1, fixed_g: 5, custom: 0, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDB, e: 1, fixed_g: 5, custom: 1, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // skipped: #ud not supported by nasmtests in compiled code
{ opcode: 0xDB, e: 1, fixed_g: 6, custom: 0, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDB, e: 1, fixed_g: 7, custom: 0, is_fpu: 1, task_switch_test: 1, },
@ -323,7 +323,7 @@ const encodings = [
{ opcode: 0xDD, e: 1, fixed_g: 2, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDD, e: 1, fixed_g: 3, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDD, e: 1, fixed_g: 4, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1, }, // frstor
{ opcode: 0xDD, e: 1, fixed_g: 5, custom: 0, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDD, e: 1, fixed_g: 5, custom: 1, is_fpu: 1, task_switch_test: 1, only_reg: 1, }, // skipped: #ud not supported by nasmtests in compiled code
{ opcode: 0xDD, e: 1, fixed_g: 6, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1, }, // fsave
{ opcode: 0xDD, e: 1, fixed_g: 7, custom: 0, is_fpu: 1, task_switch_test: 1, },
@ -340,7 +340,8 @@ const encodings = [
{ opcode: 0xDF, e: 1, fixed_g: 1, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // unimplemented: fisttp (sse3)
{ opcode: 0xDF, e: 1, fixed_g: 2, custom: 1, is_fpu: 1, task_switch_test: 1 },
{ opcode: 0xDF, e: 1, fixed_g: 3, custom: 1, is_fpu: 1, task_switch_test: 1 },
{ opcode: 0xDF, e: 1, fixed_g: 4, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // unimplemented: Binary Coded Decimals
{ opcode: 0xDF, e: 1, fixed_g: 4, custom: 1, is_fpu: 1, task_switch_test: 1, skip: 1 }, // unimplemented (mem): Binary Coded Decimals
// skipped (reg): #ud not supported by nasmtests in compiled code
{ opcode: 0xDF, e: 1, fixed_g: 5, custom: 1, is_fpu: 1, task_switch_test: 1, },
{ opcode: 0xDF, e: 1, fixed_g: 6, custom: 0, is_fpu: 1, task_switch_test: 1, only_reg: 1 }, // unimplemented: Binary Coded Decimals
{ opcode: 0xDF, e: 1, fixed_g: 7, custom: 1, is_fpu: 1, task_switch_test: 1, only_mem: 1 }, // skipped: #ud not supported by nasmtests in compiled code

54
src/rust/jit_instructions.rs
View file

@ -1927,6 +1927,15 @@ pub fn instr_D9_0_reg_jit(ctx: &mut JitContext, r: u32) {
codegen::gen_call_fn1_f64(ctx.builder, "fpu_push");
}
pub fn instr_D9_1_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_trigger_ud(ctx);
}
pub fn instr_D9_1_reg_jit(ctx: &mut JitContext, r: u32) {
ctx.builder.instruction_body.const_i32(r as i32);
codegen::gen_call_fn1(ctx.builder, "fpu_fxch");
}
pub fn instr_D9_2_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
let address_local = ctx.builder.set_new_local();
@ -1959,6 +1968,17 @@ pub fn instr_D9_3_reg_jit(ctx: &mut JitContext, r: u32) {
codegen::gen_fn1_const(ctx.builder, "fpu_fstp", r);
}
pub fn instr_D9_4_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_call_fn1(ctx.builder, "fpu_fldenv");
// XXX: generated because fldenv might page-fault, but doesn't generate a proper block boundary
ctx.builder.instruction_body.return_();
}
pub fn instr_D9_4_reg_jit(ctx: &mut JitContext, r: u32) {
ctx.builder.instruction_body.const_i32(r as i32);
codegen::gen_call_fn1(ctx.builder, "instr_D9_4_reg");
}
pub fn instr_D9_5_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
ctx.builder
.instruction_body
@ -2027,6 +2047,17 @@ pub fn instr_DB_3_reg_jit(ctx: &mut JitContext, r: u32) {
codegen::gen_fn1_const(ctx.builder, "instr_DB_3_reg", r);
}
pub fn instr_DB_5_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_call_fn1(ctx.builder, "fpu_fldm80");
// XXX: generated because fpu_fldm80 might page-fault, but doesn't generate a proper block boundary
ctx.builder.instruction_body.return_();
}
pub fn instr_DB_5_reg_jit(ctx: &mut JitContext, r: u32) {
ctx.builder.instruction_body.const_i32(r as i32);
codegen::gen_call_fn1(ctx.builder, "fpu_fucomi");
}
fn instr_group_DC_mem_jit(ctx: &mut JitContext, modrm_byte: u8, op: &str) {
ctx.builder.instruction_body.const_i32(0);
codegen::gen_modrm_resolve(ctx, modrm_byte);
@ -2131,6 +2162,15 @@ pub fn instr_DD_3_reg_jit(ctx: &mut JitContext, r: u32) {
codegen::gen_fn1_const(ctx.builder, "fpu_fstp", r);
}
pub fn instr_DD_5_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_trigger_ud(ctx);
}
pub fn instr_DD_5_reg_jit(ctx: &mut JitContext, r: u32) {
ctx.builder.instruction_body.const_i32(r as i32);
codegen::gen_call_fn1(ctx.builder, "fpu_fucomp");
}
fn instr_group_DE_mem_jit(ctx: &mut JitContext, modrm_byte: u8, op: &str) {
ctx.builder.instruction_body.const_i32(0);
codegen::gen_modrm_resolve(ctx, modrm_byte);
@ -2240,6 +2280,20 @@ pub fn instr_DF_3_reg_jit(ctx: &mut JitContext, r: u32) {
codegen::gen_fn1_const(ctx.builder, "fpu_fstp", r);
}
pub fn instr_DF_4_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
dbg_log!("fbld");
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_trigger_ud(ctx);
}
pub fn instr_DF_4_reg_jit(ctx: &mut JitContext, r: u32) {
if r == 0 {
codegen::gen_fn0_const(ctx.builder, "fpu_fnstsw_reg");
}
else {
codegen::gen_trigger_ud(ctx);
};
}
pub fn instr_DF_5_mem_jit(ctx: &mut JitContext, modrm_byte: u8) {
codegen::gen_modrm_resolve(ctx, modrm_byte);
codegen::gen_safe_read64(ctx);