Initial APIC implementation, incomplete
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src/apic.js
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267
src/apic.js
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"use strict";
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/** @const */
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var APIC_ADDRESS = 0xFEE00000;
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/** @const */
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var IOAPIC_ADDRESS = 0xFEC00000;
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/** @const */
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var IOREGSEL = 0;
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/** @const */
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var IOWIN = 0x10;
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/** @const */
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var IOAPIC_IRQ_COUNT = 24;
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/** @const */
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var IOAPIC_ID = 0; // must match value in seabios
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/**
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* @constructor
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* @param {CPU} cpu
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*/
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function APIC(cpu)
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{
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this.cpu = cpu;
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var io = cpu.io;
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this.ioredtlb = new Int32Array(0x10 + IOAPIC_IRQ_COUNT * 2);
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for(var i = 0; i < this.ioredtlb.length; i += 2)
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{
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// disable interrupts
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this.ioredtlb[i] = 1 << 16;
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}
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this.irqs = [];
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this.ioapic_id = IOAPIC_ID;
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this.lapic_tpr = 0;
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this.lapic_icr = new Int32Array(2);
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io.mmap_register(APIC_ADDRESS, 0x100000,
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function(addr)
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{
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dbg_trace();
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dbg_log("unsupported read8 from apic: " + h(addr), LOG_APIC);
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return 0;
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},
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function(addr, value)
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{
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dbg_trace();
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dbg_log("unsupported write8 from apic: " + h(addr) + " <- " + h(value), LOG_APIC);
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},
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function(addr)
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{
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addr = addr - APIC_ADDRESS | 0;
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switch(addr)
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{
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case 0x30:
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// version
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return 0x50011
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case 0x80:
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// tpr
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return me.lapic_tpr;
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case 0x300:
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return me.lapic_icr[0];
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default:
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dbg_log("APIC read32 " + h(addr), LOG_APIC);
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return 0;
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}
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},
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function(addr, value)
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{
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addr = addr - APIC_ADDRESS | 0;
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switch(addr)
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{
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case 0x80:
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// tpr
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me.lapic_tpr = value;
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break;
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case 0x300:
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me.lapic_icr[0] = value;
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break;
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default:
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dbg_log("APIC write32 " + h(addr) + " <- " + h(value, 8), LOG_APIC);
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}
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});
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this.iotable = new Int32Array(IOAPIC_IRQ_COUNT * 2);
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// IOAPIC register selection
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var ioregsel = 0;
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var me = this;
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dbg_assert(MMAP_BLOCK_SIZE >= 0x20);
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io.mmap_register(IOAPIC_ADDRESS, MMAP_BLOCK_SIZE,
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function(addr)
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{
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throw "unsupported read8 from ioapic";
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},
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function(addr, value)
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{
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throw "unsupported write8 from ioapic";
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},
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function(addr)
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{
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addr = addr - IOAPIC_ADDRESS | 0;
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if(addr === IOREGSEL)
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{
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dbg_log("Unexpected IOAPIC register read ioregsel", LOG_APIC);
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}
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else if(addr === IOWIN)
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{
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dbg_log("IOAPIC read32 " + h(ioregsel), LOG_APIC);
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return me.ioapic_read(ioregsel);
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}
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else
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{
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dbg_log("Unexpected IOAPIC register read: " + h(addr), LOG_APIC);
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return 0;
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}
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},
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function(addr, value)
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{
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addr = addr - IOAPIC_ADDRESS | 0;
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if(addr === IOREGSEL)
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{
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ioregsel = value;
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}
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else if(addr === IOWIN)
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{
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me.ioapic_write(ioregsel, value);
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}
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else
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{
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dbg_log("Unexpected IOAPIC register write: " + h(addr) + " <- " + h(value, 8), LOG_APIC);
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}
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});
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}
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APIC.prototype.check_irqs = function()
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{
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if(!this.irqs.length)
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{
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return;
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}
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var irq_number = this.irqs.pop();
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dbg_log("Handle irq " + h(irq_number), LOG_APIC);
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this.cpu.previous_ip = this.cpu.instruction_pointer;
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this.cpu.call_interrupt_vector(irq_number, false, false);
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};
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APIC.prototype.raise_irq = function(i)
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{
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//dbg_log("apic raise irq " + h(i), LOG_APIC);
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var infos = this.ioredtlb[0x10 + (i << 1)]
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if(infos & (1 << 16))
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{
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return;
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}
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this.irqs.push(infos & 0xFF);
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this.cpu.handle_irqs();
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};
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APIC.prototype.ioapic_read = function(reg)
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{
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switch(reg)
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{
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case 0:
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return this.ioapic_id << 24;
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case 1:
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return 0x11 | IOAPIC_IRQ_COUNT - 1 << 16;
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case 2:
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// Arbitration ID
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return 0;
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default:
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if(reg >= 0x10 && reg < 0x10 + 2 * IOAPIC_IRQ_COUNT)
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{
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var irq = reg - 0x10 >> 1;
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var index = reg & 1;
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if(index)
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{
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dbg_log("Read destination irq=" + h(irq), LOG_APIC);
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}
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else
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{
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dbg_log("Read config irq=" + h(irq), LOG_APIC);
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}
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return this.ioredtlb[reg];
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}
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else
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{
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dbg_log("IOAPIC register read outside of range " + h(reg), LOG_APIC);
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return 0;
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}
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}
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};
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APIC.prototype.ioapic_write = function(reg, value)
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{
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dbg_log("IOAPIC write " + h(reg) + " <- " + h(value, 8), LOG_APIC);
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switch(reg)
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{
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case 0:
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this.ioapic_id = value >>> 24;
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break;
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default:
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if(reg >= 0x10 && reg < 0x10 + 2 * IOAPIC_IRQ_COUNT)
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{
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this.ioredtlb[reg] = value;
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var irq = reg - 0x10 >> 1;
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var index = reg & 1;
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if(index)
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{
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dbg_log("Write destination " + h(value >>> 0, 8) + " irq=" + h(irq) + " dest=" + h(value >>> 24, 2), LOG_APIC);
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}
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else
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{
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var vector = value & 0xFF;
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var delivery_mode = value >> 8 & 7;
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var destination_mode = value >> 11 & 1;
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var disabled = value >> 16 & 1;
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dbg_log("Write config " + h(value >>> 0, 8) +
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" irq=" + h(irq) +
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" vector=" + h(vector, 2) +
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" delivery=" + h(delivery_mode) +
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" dmode=" + destination_mode +
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" disabled=" + disabled, LOG_APIC);
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}
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}
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else
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{
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dbg_log("IOAPIC register write outside of range " + h(reg) + ": " + h(value >>> 0, 8), LOG_APIC);
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}
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}
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};
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