321 lines
7.6 KiB
C
321 lines
7.6 KiB
C
/*
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* Generic PCI host controller as described in PCI Bus Binding to Open Firmware
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*
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* Copyright (C) 2016, Red Hat Inc, Alexander Gordeev <agordeev@redhat.com>
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.
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*/
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#include "libcflat.h"
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#include "devicetree.h"
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#include "alloc.h"
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#include "pci.h"
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#include "asm/pci.h"
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#include "asm/io.h"
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#include "pci-host-generic.h"
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#include <linux/pci_regs.h>
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static struct pci_host_bridge *pci_host_bridge;
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static int of_flags_to_pci_type(u32 of_flags)
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{
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static int type_map[] = {
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[1] = PCI_BASE_ADDRESS_SPACE_IO,
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[2] = PCI_BASE_ADDRESS_MEM_TYPE_32,
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[3] = PCI_BASE_ADDRESS_MEM_TYPE_64
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};
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int idx = (of_flags >> 24) & 0x03;
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int res;
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assert(idx > 0);
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res = type_map[idx];
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if (of_flags & 0x40000000)
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res |= PCI_BASE_ADDRESS_MEM_PREFETCH;
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return res;
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}
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static int pci_bar_type(u32 bar)
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{
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if (bar & PCI_BASE_ADDRESS_SPACE)
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return PCI_BASE_ADDRESS_SPACE_IO;
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else
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return bar & (PCI_BASE_ADDRESS_MEM_TYPE_MASK |
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PCI_BASE_ADDRESS_MEM_PREFETCH);
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}
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/*
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* Probe DT for a generic PCI host controller
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* See kernel Documentation/devicetree/bindings/pci/host-generic-pci.txt
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* and function gen_pci_probe() in drivers/pci/host/pci-host-generic.c
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*/
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static struct pci_host_bridge *pci_dt_probe(void)
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{
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struct pci_host_bridge *host;
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const void *fdt = dt_fdt();
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const struct fdt_property *prop;
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struct dt_pbus_reg base;
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struct dt_device dt_dev;
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struct dt_bus dt_bus;
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struct pci_addr_space *as;
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fdt32_t *data;
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u32 bus, bus_max;
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u32 nac, nsc, nac_root, nsc_root;
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int nr_range_cells, nr_addr_spaces;
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int ret, node, len, i;
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if (!dt_available()) {
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printf("No device tree found\n");
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return NULL;
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}
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dt_bus_init_defaults(&dt_bus);
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dt_device_init(&dt_dev, &dt_bus, NULL);
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node = fdt_path_offset(fdt, "/");
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assert(node >= 0);
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ret = dt_get_nr_cells(node, &nac_root, &nsc_root);
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assert(ret == 0);
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assert(nac_root == 1 || nac_root == 2);
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node = fdt_node_offset_by_compatible(fdt, node,
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"pci-host-ecam-generic");
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if (node == -FDT_ERR_NOTFOUND) {
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printf("No PCIe ECAM compatible controller found\n");
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return NULL;
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}
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assert(node >= 0);
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prop = fdt_get_property(fdt, node, "device_type", &len);
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assert(prop && len == 4 && !strcmp((char *)prop->data, "pci"));
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dt_device_bind_node(&dt_dev, node);
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ret = dt_pbus_get_base(&dt_dev, &base);
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assert(ret == 0);
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prop = fdt_get_property(fdt, node, "bus-range", &len);
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if (prop == NULL) {
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assert(len == -FDT_ERR_NOTFOUND);
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bus = 0x00;
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bus_max = 0xff;
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} else {
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data = (fdt32_t *)prop->data;
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bus = fdt32_to_cpu(data[0]);
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bus_max = fdt32_to_cpu(data[1]);
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assert(bus <= bus_max);
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}
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assert(bus_max < base.size / (1 << PCI_ECAM_BUS_SHIFT));
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ret = dt_get_nr_cells(node, &nac, &nsc);
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assert(ret == 0);
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assert(nac == 3 && nsc == 2);
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prop = fdt_get_property(fdt, node, "ranges", &len);
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assert(prop != NULL);
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nr_range_cells = nac + nsc + nac_root;
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nr_addr_spaces = (len / 4) / nr_range_cells;
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assert(nr_addr_spaces);
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host = malloc(sizeof(*host) +
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sizeof(host->addr_space[0]) * nr_addr_spaces);
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assert(host != NULL);
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host->start = base.addr;
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host->size = base.size;
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host->bus = bus;
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host->bus_max = bus_max;
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host->nr_addr_spaces = nr_addr_spaces;
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data = (fdt32_t *)prop->data;
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as = &host->addr_space[0];
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for (i = 0; i < nr_addr_spaces; i++) {
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/*
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* The PCI binding encodes the PCI address with three
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* cells as follows:
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*
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* PCI device bus address and flags are encoded into phys.high
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* PCI 64 bit address is encoded into phys.mid and phys.low
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*/
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as->type = of_flags_to_pci_type(fdt32_to_cpu(data[0]));
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as->pci_start = ((u64)fdt32_to_cpu(data[1]) << 32) |
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fdt32_to_cpu(data[2]);
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if (nr_range_cells == 6) {
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as->start = fdt32_to_cpu(data[3]);
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as->size = ((u64)fdt32_to_cpu(data[4]) << 32) |
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fdt32_to_cpu(data[5]);
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} else {
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as->start = ((u64)fdt32_to_cpu(data[3]) << 32) |
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fdt32_to_cpu(data[4]);
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as->size = ((u64)fdt32_to_cpu(data[5]) << 32) |
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fdt32_to_cpu(data[6]);
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}
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data += nr_range_cells;
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as++;
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}
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return host;
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}
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static bool pci_alloc_resource(struct pci_dev *dev, int bar_num, u64 *addr)
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{
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struct pci_host_bridge *host = pci_host_bridge;
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struct pci_addr_space *as = &host->addr_space[0];
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u32 bar;
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u64 size, pci_addr;
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int type, i;
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*addr = INVALID_PHYS_ADDR;
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size = pci_bar_size(dev, bar_num);
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if (!size)
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return false;
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bar = pci_bar_get(dev, bar_num);
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type = pci_bar_type(bar);
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if (type & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
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type &= ~PCI_BASE_ADDRESS_MEM_PREFETCH;
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for (i = 0; i < host->nr_addr_spaces; i++) {
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if (as->type == type)
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break;
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as++;
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}
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if (i >= host->nr_addr_spaces) {
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printf("%s: warning: can't satisfy request for ", __func__);
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pci_dev_print_id(dev);
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printf(" ");
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pci_bar_print(dev, bar_num);
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printf("\n");
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return false;
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}
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pci_addr = ALIGN(as->pci_start + as->allocated, size);
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size += pci_addr - (as->pci_start + as->allocated);
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assert(as->allocated + size <= as->size);
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*addr = pci_addr;
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as->allocated += size;
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return true;
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}
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bool pci_probe(void)
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{
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struct pci_dev pci_dev;
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pcidevaddr_t dev;
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u8 header;
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u32 cmd;
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int i;
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assert(!pci_host_bridge);
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pci_host_bridge = pci_dt_probe();
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if (!pci_host_bridge)
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return false;
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for (dev = 0; dev < PCI_DEVFN_MAX; dev++) {
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if (!pci_dev_exists(dev))
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continue;
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pci_dev_init(&pci_dev, dev);
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/* We are only interested in normal PCI devices */
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header = pci_config_readb(dev, PCI_HEADER_TYPE);
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if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
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continue;
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cmd = PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
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for (i = 0; i < PCI_BAR_NUM; i++) {
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u64 addr;
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if (pci_alloc_resource(&pci_dev, i, &addr)) {
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pci_bar_set_addr(&pci_dev, i, addr);
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if (pci_bar_is_memory(&pci_dev, i))
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cmd |= PCI_COMMAND_MEMORY;
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else
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cmd |= PCI_COMMAND_IO;
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}
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if (pci_bar_is64(&pci_dev, i))
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i++;
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}
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pci_config_writew(dev, PCI_COMMAND, cmd);
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}
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return true;
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}
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/*
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* This function is to be called from pci_translate_addr() to provide
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* mapping between this host bridge's PCI busses address and CPU physical
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* address.
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*/
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phys_addr_t pci_host_bridge_get_paddr(u64 pci_addr)
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{
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struct pci_host_bridge *host = pci_host_bridge;
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struct pci_addr_space *as = &host->addr_space[0];
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int i;
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for (i = 0; i < host->nr_addr_spaces; i++) {
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if (pci_addr >= as->pci_start &&
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pci_addr < as->pci_start + as->size)
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return as->start + (pci_addr - as->pci_start);
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as++;
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}
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return INVALID_PHYS_ADDR;
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}
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static void __iomem *pci_get_dev_conf(struct pci_host_bridge *host, int devfn)
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{
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return (void __iomem *)(unsigned long)
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host->start + (devfn << PCI_ECAM_DEVFN_SHIFT);
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}
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u8 pci_config_readb(pcidevaddr_t dev, u8 off)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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return readb(conf + off);
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}
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u16 pci_config_readw(pcidevaddr_t dev, u8 off)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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return readw(conf + off);
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}
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u32 pci_config_readl(pcidevaddr_t dev, u8 off)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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return readl(conf + off);
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}
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void pci_config_writeb(pcidevaddr_t dev, u8 off, u8 val)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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writeb(val, conf + off);
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}
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void pci_config_writew(pcidevaddr_t dev, u8 off, u16 val)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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writew(val, conf + off);
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}
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void pci_config_writel(pcidevaddr_t dev, u8 off, u32 val)
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{
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void __iomem *conf = pci_get_dev_conf(pci_host_bridge, dev);
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writel(val, conf + off);
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}
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