387 lines
8.9 KiB
C
387 lines
8.9 KiB
C
/*
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* Copyright (C) 2013, Red Hat Inc, Michael S. Tsirkin <mst@redhat.com>
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.
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*/
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#include <linux/pci_regs.h>
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#include "pci.h"
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#include "asm/pci.h"
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void pci_cap_walk(struct pci_dev *dev, pci_cap_handler_t handler)
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{
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uint8_t cap_offset;
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uint8_t cap_id;
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int count = 0;
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cap_offset = pci_config_readb(dev->bdf, PCI_CAPABILITY_LIST);
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while (cap_offset) {
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cap_id = pci_config_readb(dev->bdf, cap_offset);
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assert(cap_id < PCI_CAP_ID_MAX + 1);
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handler(dev, cap_offset, cap_id);
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cap_offset = pci_config_readb(dev->bdf, cap_offset + 1);
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/* Avoid dead loop during cap walk */
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assert(++count <= 255);
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}
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}
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void pci_msi_set_enable(struct pci_dev *dev, bool enabled)
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{
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uint16_t msi_control;
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uint16_t offset;
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offset = dev->msi_offset;
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msi_control = pci_config_readw(dev->bdf, offset + PCI_MSI_FLAGS);
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if (enabled)
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msi_control |= PCI_MSI_FLAGS_ENABLE;
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else
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msi_control &= ~PCI_MSI_FLAGS_ENABLE;
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pci_config_writew(dev->bdf, offset + PCI_MSI_FLAGS, msi_control);
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}
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bool pci_setup_msi(struct pci_dev *dev, uint64_t msi_addr, uint32_t msi_data)
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{
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uint16_t msi_control;
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uint16_t offset;
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pcidevaddr_t addr;
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assert(dev);
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if (!dev->msi_offset) {
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printf("MSI: dev %#x does not support MSI.\n", dev->bdf);
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return false;
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}
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addr = dev->bdf;
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offset = dev->msi_offset;
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msi_control = pci_config_readw(addr, offset + PCI_MSI_FLAGS);
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pci_config_writel(addr, offset + PCI_MSI_ADDRESS_LO,
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msi_addr & 0xffffffff);
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if (msi_control & PCI_MSI_FLAGS_64BIT) {
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pci_config_writel(addr, offset + PCI_MSI_ADDRESS_HI,
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(uint32_t)(msi_addr >> 32));
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pci_config_writel(addr, offset + PCI_MSI_DATA_64, msi_data);
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} else {
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pci_config_writel(addr, offset + PCI_MSI_DATA_32, msi_data);
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}
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pci_msi_set_enable(dev, true);
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return true;
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}
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void pci_cmd_set_clr(struct pci_dev *dev, uint16_t set, uint16_t clr)
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{
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uint16_t val = pci_config_readw(dev->bdf, PCI_COMMAND);
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/* No overlap is allowed */
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assert((set & clr) == 0);
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val |= set;
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val &= ~clr;
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pci_config_writew(dev->bdf, PCI_COMMAND, val);
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}
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bool pci_dev_exists(pcidevaddr_t dev)
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{
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return (pci_config_readw(dev, PCI_VENDOR_ID) != 0xffff &&
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pci_config_readw(dev, PCI_DEVICE_ID) != 0xffff);
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}
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/* Scan bus look for a specific device. Only bus 0 scanned for now. */
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pcidevaddr_t pci_find_dev(uint16_t vendor_id, uint16_t device_id)
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{
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pcidevaddr_t dev;
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for (dev = 0; dev < PCI_DEVFN_MAX; ++dev) {
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if (pci_config_readw(dev, PCI_VENDOR_ID) == vendor_id &&
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pci_config_readw(dev, PCI_DEVICE_ID) == device_id)
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return dev;
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}
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return PCIDEVADDR_INVALID;
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}
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uint32_t pci_bar_mask(uint32_t bar)
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{
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return (bar & PCI_BASE_ADDRESS_SPACE_IO) ?
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PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK;
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}
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uint32_t pci_bar_get(struct pci_dev *dev, int bar_num)
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{
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ASSERT_BAR_NUM(bar_num);
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return pci_config_readl(dev->bdf, PCI_BASE_ADDRESS_0 +
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bar_num * 4);
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}
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static phys_addr_t __pci_bar_get_addr(struct pci_dev *dev, int bar_num)
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{
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uint32_t bar = pci_bar_get(dev, bar_num);
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uint32_t mask = pci_bar_mask(bar);
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uint64_t addr = bar & mask;
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phys_addr_t phys_addr;
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if (pci_bar_is64(dev, bar_num))
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addr |= (uint64_t)pci_bar_get(dev, bar_num + 1) << 32;
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phys_addr = pci_translate_addr(dev->bdf, addr);
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assert(phys_addr != INVALID_PHYS_ADDR);
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return phys_addr;
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}
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phys_addr_t pci_bar_get_addr(struct pci_dev *dev, int bar_num)
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{
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ASSERT_BAR_NUM(bar_num);
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return dev->resource[bar_num];
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}
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void pci_bar_set_addr(struct pci_dev *dev, int bar_num, phys_addr_t addr)
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{
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int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
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assert(addr != INVALID_PHYS_ADDR);
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assert(dev->resource[bar_num] != INVALID_PHYS_ADDR);
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ASSERT_BAR_NUM(bar_num);
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if (pci_bar_is64(dev, bar_num))
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ASSERT_BAR_NUM(bar_num + 1);
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else
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assert((addr >> 32) == 0);
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pci_config_writel(dev->bdf, off, (uint32_t)addr);
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dev->resource[bar_num] = addr;
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if (pci_bar_is64(dev, bar_num)) {
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pci_config_writel(dev->bdf, off + 4, (uint32_t)(addr >> 32));
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dev->resource[bar_num + 1] = dev->resource[bar_num];
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}
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}
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/*
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* To determine the amount of address space needed by a PCI device,
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* one must save the original value of the BAR, write a value of
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* all 1's to the register, and then read it back. The amount of
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* memory can be then determined by masking the information bits,
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* performing a bitwise NOT, and incrementing the value by 1.
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*
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* The following pci_bar_size_helper() and pci_bar_size() functions
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* implement the algorithm.
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*/
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static uint32_t pci_bar_size_helper(struct pci_dev *dev, int bar_num)
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{
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int off = PCI_BASE_ADDRESS_0 + bar_num * 4;
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uint16_t bdf = dev->bdf;
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uint32_t bar, val;
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bar = pci_config_readl(bdf, off);
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pci_config_writel(bdf, off, ~0u);
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val = pci_config_readl(bdf, off);
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pci_config_writel(bdf, off, bar);
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return val;
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}
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phys_addr_t pci_bar_size(struct pci_dev *dev, int bar_num)
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{
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uint32_t bar, size;
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size = pci_bar_size_helper(dev, bar_num);
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if (!size)
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return 0;
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bar = pci_bar_get(dev, bar_num);
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size &= pci_bar_mask(bar);
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if (pci_bar_is64(dev, bar_num)) {
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phys_addr_t size64 = pci_bar_size_helper(dev, bar_num + 1);
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size64 = (size64 << 32) | size;
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return ~size64 + 1;
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} else {
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return ~size + 1;
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}
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}
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bool pci_bar_is_memory(struct pci_dev *dev, int bar_num)
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{
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uint32_t bar = pci_bar_get(dev, bar_num);
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return !(bar & PCI_BASE_ADDRESS_SPACE_IO);
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}
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bool pci_bar_is_valid(struct pci_dev *dev, int bar_num)
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{
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return dev->resource[bar_num] != INVALID_PHYS_ADDR;
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}
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bool pci_bar_is64(struct pci_dev *dev, int bar_num)
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{
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uint32_t bar = pci_bar_get(dev, bar_num);
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if (bar & PCI_BASE_ADDRESS_SPACE_IO)
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return false;
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return (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64;
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}
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void pci_bar_print(struct pci_dev *dev, int bar_num)
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{
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phys_addr_t size, start, end;
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uint32_t bar;
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if (!pci_bar_is_valid(dev, bar_num))
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return;
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bar = pci_bar_get(dev, bar_num);
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size = pci_bar_size(dev, bar_num);
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start = pci_bar_get_addr(dev, bar_num);
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end = start + size - 1;
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if (pci_bar_is64(dev, bar_num)) {
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printf("BAR#%d,%d [%" PRIx64 "-%" PRIx64 " ",
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bar_num, bar_num + 1, start, end);
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} else {
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printf("BAR#%d [%02x-%02x ",
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bar_num, (uint32_t)start, (uint32_t)end);
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}
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if (bar & PCI_BASE_ADDRESS_SPACE_IO) {
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printf("PIO");
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} else {
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printf("MEM");
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switch (bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
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case PCI_BASE_ADDRESS_MEM_TYPE_32:
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printf("32");
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break;
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case PCI_BASE_ADDRESS_MEM_TYPE_1M:
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printf("1M");
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break;
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case PCI_BASE_ADDRESS_MEM_TYPE_64:
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printf("64");
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break;
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default:
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assert(0);
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}
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}
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if (bar & PCI_BASE_ADDRESS_MEM_PREFETCH)
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printf("/p");
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printf("]");
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}
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void pci_dev_print_id(struct pci_dev *dev)
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{
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pcidevaddr_t bdf = dev->bdf;
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printf("00.%02x.%1x %04x:%04x", bdf / 8, bdf % 8,
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pci_config_readw(bdf, PCI_VENDOR_ID),
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pci_config_readw(bdf, PCI_DEVICE_ID));
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}
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static void pci_cap_print(struct pci_dev *dev, int cap_offset, int cap_id)
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{
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switch (cap_id) {
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case PCI_CAP_ID_MSI: {
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uint16_t control = pci_config_readw(dev->bdf, cap_offset + PCI_MSI_FLAGS);
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printf("\tMSI,%s-bit capability ", control & PCI_MSI_FLAGS_64BIT ? "64" : "32");
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break;
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}
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default:
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printf("\tcapability %#04x ", cap_id);
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break;
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}
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printf("at offset %#04x\n", cap_offset);
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}
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void pci_dev_print(struct pci_dev *dev)
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{
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pcidevaddr_t bdf = dev->bdf;
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uint8_t header = pci_config_readb(bdf, PCI_HEADER_TYPE);
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uint8_t progif = pci_config_readb(bdf, PCI_CLASS_PROG);
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uint8_t subclass = pci_config_readb(bdf, PCI_CLASS_DEVICE);
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uint8_t class = pci_config_readb(bdf, PCI_CLASS_DEVICE + 1);
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int i;
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pci_dev_print_id(dev);
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printf(" type %02x progif %02x class %02x subclass %02x\n",
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header, progif, class, subclass);
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pci_cap_walk(dev, pci_cap_print);
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if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_TYPE_NORMAL)
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return;
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for (i = 0; i < PCI_BAR_NUM; i++) {
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if (pci_bar_is_valid(dev, i)) {
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printf("\t");
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pci_bar_print(dev, i);
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printf("\n");
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}
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if (pci_bar_is64(dev, i))
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i++;
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}
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}
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void pci_print(void)
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{
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pcidevaddr_t devfn;
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struct pci_dev pci_dev;
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for (devfn = 0; devfn < PCI_DEVFN_MAX; ++devfn) {
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if (pci_dev_exists(devfn)) {
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pci_dev_init(&pci_dev, devfn);
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pci_dev_print(&pci_dev);
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}
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}
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}
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void pci_dev_init(struct pci_dev *dev, pcidevaddr_t bdf)
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{
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int i;
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memset(dev, 0, sizeof(*dev));
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dev->bdf = bdf;
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for (i = 0; i < PCI_BAR_NUM; i++) {
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if (pci_bar_size(dev, i)) {
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dev->resource[i] = __pci_bar_get_addr(dev, i);
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if (pci_bar_is64(dev, i)) {
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assert(i + 1 < PCI_BAR_NUM);
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dev->resource[i + 1] = dev->resource[i];
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i++;
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}
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} else {
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dev->resource[i] = INVALID_PHYS_ADDR;
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}
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}
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}
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uint8_t pci_intx_line(struct pci_dev *dev)
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{
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return pci_config_readb(dev->bdf, PCI_INTERRUPT_LINE);
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}
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static void pci_cap_setup(struct pci_dev *dev, int cap_offset, int cap_id)
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{
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switch (cap_id) {
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case PCI_CAP_ID_MSI:
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dev->msi_offset = cap_offset;
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break;
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}
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}
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void pci_enable_defaults(struct pci_dev *dev)
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{
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/* Enable device DMA operations */
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pci_cmd_set_clr(dev, PCI_COMMAND_MASTER, 0);
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pci_cap_walk(dev, pci_cap_setup);
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}
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