575 lines
15 KiB
JavaScript
575 lines
15 KiB
JavaScript
"use strict";
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/** @const */
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var PIC_LOG_VERBOSE = false;
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/**
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* Programmable Interrupt Controller
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* http://stanislavs.org/helppc/8259.html
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*
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* @constructor
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* @param {CPU} cpu
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* @param {PIC=} master
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*/
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function PIC(cpu, master)
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{
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/**
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* all irqs off
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* @type {number}
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*/
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this.irq_mask = 0;
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/**
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* @type {number}
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*
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* Bogus default value (both master and slave mapped to 0).
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* Will be initialized by the BIOS
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*/
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this.irq_map = 0;
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/**
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* in-service register
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* Holds interrupts that are currently being serviced
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* @type {number}
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*/
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this.isr = 0;
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/**
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* interrupt request register
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* Holds interrupts that have been requested
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* @type {number}
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*/
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this.irr = 0;
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this.irq_value = 0;
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/**
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* @type {number}
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*/
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this.requested_irq = -1;
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this.master = master;
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this.is_master = this.master === undefined;
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this.slave = undefined;
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this.name = this.is_master ? "master" : "slave ";
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this.expect_icw4 = false;
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this.state = 0;
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this.read_isr = 0;
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this.auto_eoi = 1;
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this.special_mask_mode = 0;
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this.elcr = 0;
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this.cpu = cpu;
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// Checking for callable interrupts:
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// (cpu changes interrupt flag) -> cpu.handle_irqs -> pic.check_irqs -> cpu.pic_call_irq
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// (pic changes isr/irr) -> cpu.handle_irqs -> ...
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// triggering irqs:
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// (io device has irq) -> cpu.device_raise_irq -> pic.set_irq -> cpu.handle_irqs -> (see above)
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if(this.is_master)
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{
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this.slave = new PIC(this.cpu, this);
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this.check_irqs = function()
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{
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if(this.requested_irq >= 0)
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{
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PIC_LOG_VERBOSE && dbg_log("master> Already requested irq: " + this.requested_irq, LOG_PIC);
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this.cpu.handle_irqs();
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return;
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}
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var enabled_irr = this.irr & this.irq_mask;
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if(!enabled_irr)
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("master> no unmasked irrs. irr=" + h(this.irr, 2) +
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" mask=" + h(this.irq_mask & 0xff, 2) + " isr=" + h(this.isr, 2), LOG_PIC);
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}
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return;
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}
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var irq_mask = enabled_irr & -enabled_irr;
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var special_mask = this.special_mask_mode ? this.irq_mask : -1;
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if(this.isr && (this.isr & -this.isr & special_mask) <= irq_mask)
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{
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// wait for eoi of higher or same priority interrupt
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dbg_log("master> higher prio: isr=" + h(this.isr, 2) +
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" mask=" + h(this.irq_mask & 0xff, 2) + " irq=" + h(irq_mask, 2), LOG_PIC);
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return;
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}
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dbg_assert(irq_mask !== 0);
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var irq_number = v86util.int_log2_byte(irq_mask);
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dbg_assert(irq_mask === (1 << irq_number));
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PIC_LOG_VERBOSE && dbg_log("master> request irq " + irq_number, LOG_PIC);
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this.requested_irq = irq_number;
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this.cpu.handle_irqs();
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};
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this.acknowledge_irq = function()
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{
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if(this.requested_irq === -1)
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{
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return;
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}
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if(this.irr === 0)
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{
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PIC_LOG_VERBOSE && dbg_log("master> spurious requested=" + this.requested_irq, LOG_PIC);
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this.requested_irq = -1;
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//this.cpu.pic_call_irq(this.irq_map | 7);
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return;
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}
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dbg_assert(this.irr); // spurious
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dbg_assert(this.requested_irq >= 0);
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var irq_mask = 1 << this.requested_irq;
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if((this.elcr & irq_mask) === 0) // not in level mode
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{
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this.irr &= ~irq_mask;
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}
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if(!this.auto_eoi)
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{
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this.isr |= irq_mask;
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}
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PIC_LOG_VERBOSE && dbg_log("master> acknowledge " + this.requested_irq, LOG_PIC);
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if(this.requested_irq === 2)
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{
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this.slave.acknowledge_irq();
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}
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else
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{
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this.cpu.pic_call_irq(this.irq_map | this.requested_irq);
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}
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this.requested_irq = -1;
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this.check_irqs();
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};
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}
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else
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{
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// is slave
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this.check_irqs = function()
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{
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if(this.requested_irq >= 0)
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{
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PIC_LOG_VERBOSE && dbg_log("slave > Already requested irq: " + this.requested_irq, LOG_PIC);
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this.cpu.handle_irqs();
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return;
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}
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var enabled_irr = this.irr & this.irq_mask;
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if(!enabled_irr)
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("slave > no unmasked irrs. irr=" + h(this.irr, 2) +
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" mask=" + h(this.irq_mask & 0xff, 2) + " isr=" + h(this.isr, 2), LOG_PIC);
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}
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return;
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}
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var irq_mask = enabled_irr & -enabled_irr;
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var special_mask = this.special_mask_mode ? this.irq_mask : -1;
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if(this.isr && (this.isr & -this.isr & special_mask) <= irq_mask)
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{
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// wait for eoi of higher or same priority interrupt
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PIC_LOG_VERBOSE && dbg_log("slave > higher prio: isr=" + h(this.isr, 2) + " irq=" + h(irq_mask, 2), LOG_PIC);
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return;
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}
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dbg_assert(irq_mask !== 0);
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var irq_number = v86util.int_log2_byte(irq_mask);
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dbg_assert(irq_mask === (1 << irq_number));
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PIC_LOG_VERBOSE && dbg_log("slave > request irq " + irq_number, LOG_PIC);
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this.requested_irq = irq_number;
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this.master.set_irq(2);
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};
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this.acknowledge_irq = function()
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{
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if(this.requested_irq === -1)
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{
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return;
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}
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if(this.irr === 0)
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{
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PIC_LOG_VERBOSE && dbg_log("slave > spurious requested=" + this.requested_irq, LOG_PIC);
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this.requested_irq = -1;
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this.master.irq_value &= ~(1 << 2);
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this.cpu.pic_call_irq(this.irq_map | 7);
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return;
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}
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dbg_assert(this.irr); // spurious
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dbg_assert(this.requested_irq >= 0);
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var irq_mask = 1 << this.requested_irq;
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if((this.elcr & irq_mask) === 0) // not in level mode
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{
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this.irr &= ~irq_mask;
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}
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if(!this.auto_eoi)
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{
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this.isr |= irq_mask;
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}
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this.master.irq_value &= ~(1 << 2);
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PIC_LOG_VERBOSE && dbg_log("slave > acknowledge " + this.requested_irq, LOG_PIC);
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this.cpu.pic_call_irq(this.irq_map | this.requested_irq);
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this.requested_irq = -1;
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this.check_irqs();
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};
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}
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this.dump = function()
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{
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dbg_log("mask: " + h(this.irq_mask & 0xFF), LOG_PIC);
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dbg_log("base: " + h(this.irq_map), LOG_PIC);
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dbg_log("requested: " + h(this.irr), LOG_PIC);
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dbg_log("serviced: " + h(this.isr), LOG_PIC);
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if(this.is_master)
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{
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this.slave.dump();
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}
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};
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var io_base;
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var iobase_high;
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if(this.is_master)
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{
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io_base = 0x20;
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iobase_high = 0x4D0;
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}
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else
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{
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io_base = 0xA0;
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iobase_high = 0x4D1;
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}
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this.cpu.io.register_write(io_base, this, this.port20_write);
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this.cpu.io.register_read(io_base, this, this.port20_read);
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this.cpu.io.register_write(io_base | 1, this, this.port21_write);
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this.cpu.io.register_read(io_base | 1, this, this.port21_read);
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this.cpu.io.register_write(iobase_high, this, this.port4D0_write);
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this.cpu.io.register_read(iobase_high, this, this.port4D0_read);
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if(this.is_master)
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{
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this.set_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 16);
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if(irq_number >= 8)
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{
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this.slave.set_irq(irq_number - 8);
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return;
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}
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var irq_mask = 1 << irq_number;
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if((this.irq_value & irq_mask) === 0)
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("master> set irq " + irq_number, LOG_PIC);
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}
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this.irr |= irq_mask;
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this.irq_value |= irq_mask;
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this.check_irqs();
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}
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else
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("master> set irq " + irq_number + ": already set!", LOG_PIC);
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}
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}
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};
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this.clear_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 16);
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("master> clear irq " + irq_number, LOG_PIC);
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}
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if(irq_number >= 8)
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{
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this.slave.clear_irq(irq_number - 8);
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return;
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}
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var irq_mask = 1 << irq_number;
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if(this.irq_value & irq_mask)
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{
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this.irq_value &= ~irq_mask;
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this.irr &= ~irq_mask;
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this.check_irqs();
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}
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};
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}
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else
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{
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this.set_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 8);
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var irq_mask = 1 << irq_number;
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if((this.irq_value & irq_mask) === 0)
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("slave > set irq " + irq_number, LOG_PIC);
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}
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this.irr |= irq_mask;
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this.irq_value |= irq_mask;
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this.check_irqs();
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}
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else
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{
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("slave > set irq " + irq_number + ": already set!", LOG_PIC);
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}
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}
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};
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this.clear_irq = function(irq_number)
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{
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dbg_assert(irq_number >= 0 && irq_number < 8);
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("slave > clear irq " + irq_number, LOG_PIC);
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}
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var irq_mask = 1 << irq_number;
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if(this.irq_value & irq_mask)
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{
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this.irq_value &= ~irq_mask;
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this.irr &= ~irq_mask;
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this.check_irqs();
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}
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};
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}
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this.get_isr = function()
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{
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return this.isr;
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};
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}
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PIC.prototype.get_state = function()
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{
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var state = [];
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state[0] = this.irq_mask;
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state[1] = this.irq_map;
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state[2] = this.isr;
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state[3] = this.irr;
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state[4] = this.is_master;
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state[5] = this.slave;
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state[6] = this.expect_icw4;
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state[7] = this.state;
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state[8] = this.read_isr;
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state[9] = this.auto_eoi;
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state[10] = this.elcr;
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return state;
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};
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PIC.prototype.set_state = function(state)
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{
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this.irq_mask = state[0];
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this.irq_map = state[1];
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this.isr = state[2];
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this.irr = state[3];
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this.is_master = state[4];
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this.slave && this.slave.set_state(state[5]);
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this.expect_icw4 = state[6];
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this.state = state[7];
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this.read_isr = state[8];
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this.auto_eoi = state[9];
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this.elcr = state[10];
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};
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PIC.prototype.port20_write = function(data_byte)
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{
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//dbg_log("20 write: " + h(data_byte), LOG_PIC);
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if(data_byte & 0x10) // xxxx1xxx
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{
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// icw1
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dbg_log("icw1 = " + h(data_byte), LOG_PIC);
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this.isr = 0;
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this.irr = 0;
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this.irq_mask = 0;
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this.irq_value = 0;
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this.auto_eoi = 1;
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this.requested_irq = -1;
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this.expect_icw4 = data_byte & 1;
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this.state = 1;
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}
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else if(data_byte & 8) // xxx01xxx
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{
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// ocw3
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dbg_log("ocw3: " + h(data_byte), LOG_PIC);
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if(data_byte & 2)
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{
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this.read_isr = data_byte & 1;
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}
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if(data_byte & 4)
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{
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dbg_assert(false, "unimplemented: polling", LOG_PIC);
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}
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if(data_byte & 0x40)
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{
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this.special_mask_mode = (data_byte & 0x20) === 0x20;
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dbg_log("special mask mode: " + this.special_mask_mode, LOG_PIC);
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}
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}
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else // xxx00xxx
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{
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// ocw2
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// end of interrupt
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dbg_log("eoi: " + h(data_byte) + " (" + this.name + ")", LOG_PIC);
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var eoi_type = data_byte >> 5;
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if(eoi_type === 1)
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{
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// non-specific eoi
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this.isr &= this.isr - 1;
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dbg_log("new isr: " + h(this.isr, 2), LOG_PIC);
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}
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else if(eoi_type === 3)
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{
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// specific eoi
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this.isr &= ~(1 << (data_byte & 7));
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}
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else if((data_byte & 0xC8) === 0xC0)
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{
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// os2 v4
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let priority = data_byte & 7;
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dbg_log("lowest priority: " + h(priority), LOG_PIC);
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}
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else
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{
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dbg_log("Unknown eoi: " + h(data_byte), LOG_PIC);
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dbg_assert(false);
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this.isr &= this.isr - 1;
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}
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this.check_irqs();
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}
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};
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PIC.prototype.port20_read = function()
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{
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if(this.read_isr)
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{
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dbg_log("read port 20h (isr): " + h(this.isr), LOG_PIC);
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return this.isr;
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}
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else
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{
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dbg_log("read port 20h (irr): " + h(this.irr), LOG_PIC);
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return this.irr;
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}
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};
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PIC.prototype.port21_write = function(data_byte)
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{
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//dbg_log("21 write: " + h(data_byte), LOG_PIC);
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if(this.state === 0)
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{
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if(this.expect_icw4)
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{
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// icw4
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this.expect_icw4 = false;
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this.auto_eoi = data_byte & 2;
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dbg_log("icw4: " + h(data_byte) + " autoeoi=" + this.auto_eoi, LOG_PIC);
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if((data_byte & 1) === 0)
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{
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dbg_assert(false, "unimplemented: not 8086 mode", LOG_PIC);
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}
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}
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else
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{
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// ocw1
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this.irq_mask = ~data_byte;
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if(PIC_LOG_VERBOSE)
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{
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dbg_log("interrupt mask: " + (this.irq_mask & 0xFF).toString(2) +
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" (" + this.name + ")", LOG_PIC);
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}
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this.check_irqs();
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}
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}
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else if(this.state === 1)
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{
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// icw2
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this.irq_map = data_byte;
|
|
dbg_log("interrupts are mapped to " + h(this.irq_map) +
|
|
" (" + this.name + ")", LOG_PIC);
|
|
this.state++;
|
|
}
|
|
else if(this.state === 2)
|
|
{
|
|
// icw3
|
|
this.state = 0;
|
|
dbg_log("icw3: " + h(data_byte), LOG_PIC);
|
|
}
|
|
};
|
|
|
|
PIC.prototype.port21_read = function()
|
|
{
|
|
dbg_log("21h read " + h(~this.irq_mask & 0xff), LOG_PIC);
|
|
return ~this.irq_mask & 0xFF;
|
|
};
|
|
|
|
PIC.prototype.port4D0_read = function()
|
|
{
|
|
dbg_log("elcr read: " + h(this.elcr, 2), LOG_PIC);
|
|
return this.elcr;
|
|
};
|
|
|
|
PIC.prototype.port4D0_write = function(value)
|
|
{
|
|
dbg_log("elcr write: " + h(value, 2), LOG_PIC);
|
|
// set by seabios to 00 0C (only set for pci interrupts)
|
|
this.elcr = value;
|
|
};
|
|
|