8222d2e6e0
restore memcpy comment
delete all the things!
fix jshint issues
restore memcpy comment
remove duplicate fxsave assignment
Count cache drops
Use already available physical address instead of calling read_imm8
Remove useless assertion
Just move around to reduce later diff
Run jit paging test with assertions enabled
Run jit-paging test on CI
Extend jit-paging test
Fix deleting invalidated code across memory pages
Add jit-paging test to gitlab ci
Remove jit_in_progress
Clean up old comments, use bool for jit_jump
Fix state image not begin garbage collected
Add ENABLE_PROFILER_TIMES to configure slow profiling times
Move to jit_generate and jit_run_interpreted to separate function
Add missing struct field
Fix: Don't write jit cache entry until no more faults can happen
Download image for jit paging test
Add missing initialiser
Mark jit_{generate,run_interpreted} as static
Specify full path to profiler.h
Clean up duplicate/missing declaration after rebase
mmap error handling, line length and fix some warnings
remove further unused code
move js imports to single header file
353 lines
8.6 KiB
JavaScript
353 lines
8.6 KiB
JavaScript
"use strict";
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// http://download.intel.com/design/chipsets/datashts/29056601.pdf
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/** @const */
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var IOAPIC_ADDRESS = 0xFEC00000;
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/** @const */
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var IOREGSEL = 0;
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/** @const */
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var IOWIN = 0x10;
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/** @const */
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var IOAPIC_IRQ_COUNT = 24;
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/** @const */
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var IOAPIC_ID = 0; // must match value in seabios
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/** @const */
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var IOAPIC_CONFIG_TRIGGER_MODE_LEVEL = 1 << 15;
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/** @const */
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var IOAPIC_CONFIG_MASKED = 1 << 16;
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/** @const */
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var IOAPIC_CONFIG_DELIVS = 1 << 12;
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/** @const */
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var IOAPIC_CONFIG_REMOTE_IRR = 1 << 14;
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/** @const */
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var IOAPIC_CONFIG_READONLY_MASK = IOAPIC_CONFIG_REMOTE_IRR | IOAPIC_CONFIG_DELIVS | 0xFFFE0000;
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/** @const */
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var IOAPIC_DELIVERY_FIXED = 0;
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/** @const */
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var IOAPIC_DELIVERY_LOWEST_PRIORITY = 1;
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/** @const */
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var IOAPIC_DELIVERY_NMI = 4;
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/** @const */
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var IOAPIC_DELIVERY_INIT = 5;
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/**
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* @constructor
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* @param {CPU} cpu
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*/
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function IOAPIC(cpu)
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{
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/** @type {CPU} */
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this.cpu = cpu;
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this.ioredtbl_config = new Int32Array(IOAPIC_IRQ_COUNT);
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this.ioredtbl_destination = new Int32Array(IOAPIC_IRQ_COUNT);
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for(var i = 0; i < this.ioredtbl_config.length; i++)
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{
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// disable interrupts
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this.ioredtbl_config[i] = IOAPIC_CONFIG_MASKED;
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}
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// IOAPIC register selection
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this.ioregsel = 0;
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this.ioapic_id = IOAPIC_ID;
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this.irr = 0;
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this.irq_value = 0;
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dbg_assert(MMAP_BLOCK_SIZE >= 0x20);
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cpu.io.mmap_register(IOAPIC_ADDRESS, MMAP_BLOCK_SIZE,
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(addr) =>
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{
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dbg_assert(false, "unsupported read8 from ioapic: " + h(addr));
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return 0;
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},
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(addr, value) =>
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{
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dbg_assert(false, "unsupported write8 from ioapic: " + h(addr));
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},
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(addr) =>
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{
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addr = addr - IOAPIC_ADDRESS | 0;
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if(addr === IOREGSEL)
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{
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return this.ioregsel;
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}
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else if(addr === IOWIN)
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{
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return this.read(this.ioregsel);
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}
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else
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{
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dbg_log("Unexpected IOAPIC register read: " + h(addr), LOG_APIC);
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dbg_assert(false);
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return 0;
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}
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},
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(addr, value) =>
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{
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addr = addr - IOAPIC_ADDRESS | 0;
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if(addr === IOREGSEL)
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{
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this.ioregsel = value;
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}
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else if(addr === IOWIN)
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{
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this.write(this.ioregsel, value);
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}
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else
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{
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dbg_log("Unexpected IOAPIC register write: " + h(addr) + " <- " + h(value >>> 0, 8), LOG_APIC);
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dbg_assert(false);
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}
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});
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}
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IOAPIC.prototype.remote_eoi = function(vector)
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{
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for(var i = 0; i < IOAPIC_IRQ_COUNT; i++)
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{
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var config = this.ioredtbl_config[i];
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if((config & 0xFF) === vector && (config & IOAPIC_CONFIG_REMOTE_IRR))
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{
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dbg_log("Clear remote IRR for irq=" + h(i), LOG_APIC);
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this.ioredtbl_config[i] &= ~IOAPIC_CONFIG_REMOTE_IRR;
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this.check_irq(i);
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}
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}
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};
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IOAPIC.prototype.check_irq = function(irq)
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{
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var mask = 1 << irq;
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if((this.irr & mask) === 0)
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{
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return;
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}
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var config = this.ioredtbl_config[irq];
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if((config & IOAPIC_CONFIG_MASKED) === 0)
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{
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var delivery_mode = config >> 8 & 7;
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var destination_mode = config >> 11 & 1;
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var vector = config & 0xFF;
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var destination = this.ioredtbl_destination[irq] >>> 24;
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var is_level = (config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL) === IOAPIC_CONFIG_TRIGGER_MODE_LEVEL;
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if((config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL) === 0)
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{
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this.irr &= ~mask;
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}
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else
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{
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this.ioredtbl_config[irq] |= IOAPIC_CONFIG_REMOTE_IRR;
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if(config & IOAPIC_CONFIG_REMOTE_IRR)
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{
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dbg_log("No route: level interrupt and remote IRR still set", LOG_APIC);
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return;
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}
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}
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if(delivery_mode === IOAPIC_DELIVERY_FIXED || delivery_mode === IOAPIC_DELIVERY_LOWEST_PRIORITY)
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{
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this.cpu.devices.apic.route(vector, delivery_mode, is_level, destination, destination_mode);
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}
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else
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{
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dbg_assert(false, "TODO");
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}
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this.ioredtbl_config[irq] &= ~IOAPIC_CONFIG_DELIVS;
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}
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};
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IOAPIC.prototype.set_irq = function(i)
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{
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if(i >= IOAPIC_IRQ_COUNT)
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{
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dbg_assert(false, "Bad irq: " + i, LOG_APIC);
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return;
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}
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var mask = 1 << i;
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if((this.irq_value & mask) === 0)
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{
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APIC_LOG_VERBOSE && dbg_log("apic set irq " + i, LOG_APIC);
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this.irq_value |= mask;
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var config = this.ioredtbl_config[i];
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if((config & (IOAPIC_CONFIG_TRIGGER_MODE_LEVEL|IOAPIC_CONFIG_MASKED)) ===
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IOAPIC_CONFIG_MASKED)
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{
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// edge triggered and masked
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return;
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}
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this.irr |= mask;
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this.check_irq(i);
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}
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};
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IOAPIC.prototype.clear_irq = function(i)
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{
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if(i >= IOAPIC_IRQ_COUNT)
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{
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dbg_assert(false, "Bad irq: " + i, LOG_APIC);
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return;
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}
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var mask = 1 << i;
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if((this.irq_value & mask) === mask)
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{
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this.irq_value &= ~mask;
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var config = this.ioredtbl_config[i];
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if(config & IOAPIC_CONFIG_TRIGGER_MODE_LEVEL)
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{
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this.irr &= ~mask;
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}
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}
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};
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IOAPIC.prototype.read = function(reg)
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{
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if(reg === 0)
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{
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dbg_log("IOAPIC Read id", LOG_APIC);
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return this.ioapic_id << 24;
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}
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else if(reg === 1)
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{
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dbg_log("IOAPIC Read version", LOG_APIC);
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return 0x11 | IOAPIC_IRQ_COUNT - 1 << 16;
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}
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else if(reg === 2)
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{
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dbg_log("IOAPIC Read arbitration id", LOG_APIC);
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return this.ioapic_id << 24;
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}
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else if(reg >= 0x10 && reg < 0x10 + 2 * IOAPIC_IRQ_COUNT)
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{
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var irq = reg - 0x10 >> 1;
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var index = reg & 1;
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if(index)
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{
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var value = this.ioredtbl_destination[irq];
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dbg_log("IOAPIC Read destination irq=" + h(irq) + " -> " + h(value, 8), LOG_APIC);
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}
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else
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{
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var value = this.ioredtbl_config[irq];
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dbg_log("IOAPIC Read config irq=" + h(irq) + " -> " + h(value, 8), LOG_APIC);
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}
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return value;
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}
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else
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{
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dbg_log("IOAPIC register read outside of range " + h(reg), LOG_APIC);
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dbg_assert(false);
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return 0;
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}
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};
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IOAPIC.prototype.write = function(reg, value)
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{
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//dbg_log("IOAPIC write " + h(reg) + " <- " + h(value, 8), LOG_APIC);
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if(reg === 0)
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{
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this.ioapic_id = value >>> 24 & 0x0F;
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}
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else if(reg === 1 || reg === 2)
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{
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dbg_log("Invalid write: " + reg, LOG_APIC);
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}
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else if(reg >= 0x10 && reg < 0x10 + 2 * IOAPIC_IRQ_COUNT)
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{
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var irq = reg - 0x10 >> 1;
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var index = reg & 1;
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if(index)
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{
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this.ioredtbl_destination[irq] = value & 0xFF000000;
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dbg_log("Write destination " + h(value >>> 0, 8) + " irq=" + h(irq) + " dest=" + h(value >>> 24, 2), LOG_APIC);
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}
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else
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{
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var old_value = this.ioredtbl_config[irq];
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this.ioredtbl_config[irq] = value & ~IOAPIC_CONFIG_READONLY_MASK | old_value & IOAPIC_CONFIG_READONLY_MASK;
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var vector = value & 0xFF;
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var delivery_mode = value >> 8 & 7;
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var destination_mode = value >> 11 & 1;
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var is_level = value >> 15 & 1;
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var disabled = value >> 16 & 1;
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dbg_log("Write config " + h(value >>> 0, 8) +
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" irq=" + h(irq) +
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" vector=" + h(vector, 2) +
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" deliverymode=" + DELIVERY_MODES[delivery_mode] +
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" destmode=" + DESTINATION_MODES[destination_mode] +
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" is_level=" + is_level +
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" disabled=" + disabled, LOG_APIC);
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this.check_irq(irq);
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}
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}
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else
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{
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dbg_log("IOAPIC register write outside of range " + h(reg) + ": " + h(value >>> 0, 8), LOG_APIC);
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dbg_assert(false);
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}
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};
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IOAPIC.prototype.get_state = function()
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{
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var state = [];
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state[0] = this.ioredtbl_config;
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state[1] = this.ioredtbl_destination;
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state[2] = this.ioregsel;
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state[3] = this.ioapic_id;
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state[4] = this.irr;
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state[5] = this.irq_value;
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return state;
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};
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IOAPIC.prototype.set_state = function(state)
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{
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this.ioredtbl_config = state[0];
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this.ioredtbl_destination = state[1];
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this.ioregsel = state[2];
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this.ioapic_id = state[3];
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this.irr = state[4];
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this.irq_value = state[5];
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};
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