a8308b988d
This changes registers to be temporarily stored in wasm locals, across
each complete wasm module. Registers are moved from memory to locals
upon entering the wasm module and moved from locals to memory upon
leaving. Additionally, calls to functions that modify registers are
wrapped between moving registers to memory before and moving back to
locals after. This affects:
1. All non-custom instructions
2. safe_{read,write}_slow, since it may page fault (the slow path of all memory accesses)
3. task_switch_test* and trigger_ud
4. All block boundaries
5. The fallback functions of gen_safe_read_write (read-modify-write memory accesses)
The performance benefits are currently mostly eaten up by 1. and 4. (if
one calculates the total number of read/writes to registers in memory,
they are higher after this patch, as each instructions of typ 1. or 4.
requires moving all 8 register twice). This can be improved later by the
relatively mechanical work of making instructions custom (not
necessarily full code generation, only the part of the instruction where
registers are accessed). Multi-page wasm module generation will
significantly reduce the number of type 4. instructions.
Due to 2., the overall code size has significantly increased. This case
(the slow path of memory access) is often generated but rarely executed.
These moves can be removed in a later patch by a different scheme for
safe_{read,write}_slow, which has been left out of this patch for
simplicity of reviewing.
This also simplifies our code generation for storing registers, as
instructions_body.const_i32(register_offset);
// some computations ...
instruction_body.store_i32();
turns into:
// some computations ...
write_register(register_index);
I.e., a prefix is not necessary anymore as locals are indexed directly.
Further patches will allow getting rid of some temporary locals, as
registers now can be used directly.
490 lines
14 KiB
JavaScript
Executable file
490 lines
14 KiB
JavaScript
Executable file
#!/usr/bin/env node
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"use strict";
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const fs = require("fs");
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const path = require("path");
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const x86_table = require("./x86_table");
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const rust_ast = require("./rust_ast");
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const { hex, mkdirpSync, get_switch_value, get_switch_exist, finalize_table_rust } = require("./util");
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const OUT_DIR = path.join(__dirname, "..", "src/rust/gen/");
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mkdirpSync(OUT_DIR);
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const table_arg = get_switch_value("--table");
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const gen_all = get_switch_exist("--all");
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const to_generate = {
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analyzer: gen_all || table_arg === "analyzer",
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analyzer0f_16: gen_all || table_arg === "analyzer0f_16",
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analyzer0f_32: gen_all || table_arg === "analyzer0f_32",
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};
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console.assert(
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Object.keys(to_generate).some(k => to_generate[k]),
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"Pass --table [analyzer|analyzer0f_16|analyzer0f_32] or --all to pick which tables to generate"
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);
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gen_table();
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function gen_read_imm_call(op, size_variant)
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{
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let size = (op.os || op.opcode % 2 === 1) ? size_variant : 8;
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if(op.imm8 || op.imm8s || op.imm16 || op.imm1632 || op.imm32 || op.immaddr)
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{
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if(op.imm8)
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{
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return "cpu.read_imm8()";
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}
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else if(op.imm8s)
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{
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return "cpu.read_imm8s()";
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}
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else
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{
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if(op.immaddr)
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{
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// immaddr: depends on address size
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return "cpu.read_moffs()";
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}
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else
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{
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console.assert(op.imm1632 || op.imm16 || op.imm32);
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if(op.imm1632 && size === 16 || op.imm16)
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{
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return "cpu.read_imm16()";
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}
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else
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{
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console.assert(op.imm1632 && size === 32 || op.imm32);
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return "cpu.read_imm32()";
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}
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}
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}
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}
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else
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{
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return undefined;
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}
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}
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function gen_call(name, args)
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{
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args = args || [];
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return `${name}(${args.join(", ")});`;
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}
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/*
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* Current naming scheme:
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* instr(16|32|)_(66|F2|F3)?0F?[0-9a-f]{2}(_[0-7])?(_mem|_reg|)
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*/
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function make_instruction_name(encoding, size)
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{
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const suffix = encoding.os ? String(size) : "";
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const opcode_hex = hex(encoding.opcode & 0xFF, 2);
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const first_prefix = (encoding.opcode & 0xFF00) === 0 ? "" : hex(encoding.opcode >> 8 & 0xFF, 2);
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const second_prefix = (encoding.opcode & 0xFF0000) === 0 ? "" : hex(encoding.opcode >> 16 & 0xFF, 2);
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const fixed_g_suffix = encoding.fixed_g === undefined ? "" : `_${encoding.fixed_g}`;
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console.assert(first_prefix === "" || first_prefix === "0F" || first_prefix === "F2" || first_prefix === "F3");
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console.assert(second_prefix === "" || second_prefix === "66" || second_prefix === "F2" || second_prefix === "F3");
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return `instr${suffix}_${second_prefix}${first_prefix}${opcode_hex}${fixed_g_suffix}`;
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}
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function gen_instruction_body(encodings, size)
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{
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const encoding = encodings[0];
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let has_66 = [];
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let has_F2 = [];
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let has_F3 = [];
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let no_prefix = [];
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for(let e of encodings)
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{
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if((e.opcode >>> 16) === 0x66) has_66.push(e);
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else if((e.opcode >>> 8 & 0xFF) === 0xF2 || (e.opcode >>> 16) === 0xF2) has_F2.push(e);
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else if((e.opcode >>> 8 & 0xFF) === 0xF3 || (e.opcode >>> 16) === 0xF3) has_F3.push(e);
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else no_prefix.push(e);
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}
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if(has_F2.length || has_F3.length)
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{
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console.assert((encoding.opcode & 0xFF0000) === 0 || (encoding.opcode & 0xFF00) === 0x0F00);
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}
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if(has_66.length)
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{
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console.assert((encoding.opcode & 0xFF00) === 0x0F00);
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}
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const code = [];
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if(encoding.e)
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{
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code.push("let modrm_byte = cpu.read_imm8();");
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}
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if(has_66.length || has_F2.length || has_F3.length)
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{
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const if_blocks = [];
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if(has_66.length) {
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const body = gen_instruction_body_after_prefix(has_66, size);
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if_blocks.push({ condition: "cpu.prefixes & ::prefix::PREFIX_66 != 0", body, });
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}
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if(has_F2.length) {
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const body = gen_instruction_body_after_prefix(has_F2, size);
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if_blocks.push({ condition: "cpu.prefixes & ::prefix::PREFIX_F2 != 0", body, });
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}
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if(has_F3.length) {
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const body = gen_instruction_body_after_prefix(has_F3, size);
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if_blocks.push({ condition: "cpu.prefixes & ::prefix::PREFIX_F3 != 0", body, });
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}
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const else_block = {
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body: gen_instruction_body_after_prefix(no_prefix, size),
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};
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return [].concat(
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code,
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{
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type: "if-else",
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if_blocks,
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else_block,
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}
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);
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}
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else {
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return [].concat(
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code,
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gen_instruction_body_after_prefix(encodings, size)
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);
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}
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}
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function gen_instruction_body_after_prefix(encodings, size)
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{
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const encoding = encodings[0];
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if(encoding.fixed_g !== undefined)
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{
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console.assert(encoding.e);
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// instruction with modrm byte where the middle 3 bits encode the instruction
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// group by opcode without prefix plus middle bits of modrm byte
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let cases = encodings.reduce((cases_by_opcode, case_) => {
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console.assert(typeof case_.fixed_g === "number");
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cases_by_opcode[case_.opcode & 0xFFFF | case_.fixed_g << 16] = case_;
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return cases_by_opcode;
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}, Object.create(null));
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cases = Object.values(cases).sort((e1, e2) => e1.fixed_g - e2.fixed_g);
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return [
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{
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type: "switch",
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condition: "modrm_byte >> 3 & 7",
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cases: cases.map(case_ => {
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const fixed_g = case_.fixed_g;
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const body = gen_instruction_body_after_fixed_g(case_, size);
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return {
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conditions: [fixed_g],
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body,
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};
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}),
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default_case: {
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body: [
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"analysis.ty = ::analysis::AnalysisType::BlockBoundary;",
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"analysis.no_next_instruction = true;",
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],
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}
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},
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];
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}
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else {
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console.assert(encodings.length === 1);
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return gen_instruction_body_after_fixed_g(encodings[0], size);
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}
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}
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function gen_instruction_body_after_fixed_g(encoding, size)
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{
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const imm_read = gen_read_imm_call(encoding, size);
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const instruction_postfix = [];
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if(encoding.block_boundary && !encoding.jump_offset_imm || (!encoding.custom && encoding.e))
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{
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instruction_postfix.push("analysis.ty = ::analysis::AnalysisType::BlockBoundary;");
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}
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if(encoding.no_next_instruction)
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{
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instruction_postfix.push("analysis.no_next_instruction = true;");
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}
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if(!encoding.prefix)
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{
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if(encoding.custom && !encoding.unguarded_register || encoding.no_register)
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{
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instruction_postfix.push("analysis.unguarded_register = false;");
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}
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else
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{
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instruction_postfix.push("analysis.unguarded_register = true;");
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}
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}
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if(encoding.prefix)
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{
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const instruction_name = "::analysis::" + make_instruction_name(encoding, size) + "_analyze";
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const args = ["cpu", "analysis"];
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console.assert(!imm_read);
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return [].concat(
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gen_call(instruction_name, args),
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instruction_postfix
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);
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}
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else if(encoding.e)
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{
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// instruction with modrm byte where the middle 3 bits encode a register
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if(encoding.ignore_mod)
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{
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console.assert(!imm_read, "Unexpected instruction (ignore mod with immediate value)");
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// Has modrm byte, but the 2 mod bits are ignored and both
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// operands are always registers (0f20-0f24)
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return instruction_postfix;
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}
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else
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{
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return [].concat(
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{
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type: "if-else",
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if_blocks: [{
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condition: "modrm_byte < 0xC0",
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body: [
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gen_call("::analysis::modrm_analyze", ["cpu", "modrm_byte"])
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],
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}],
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},
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imm_read ? [imm_read + ";"] : [],
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instruction_postfix
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);
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}
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}
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else
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{
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// instruction without modrm byte or prefix
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const body = [];
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if(imm_read)
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{
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if(encoding.jump_offset_imm)
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{
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body.push("let jump_offset = " + imm_read + ";");
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if(encoding.conditional_jump)
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{
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console.assert((encoding.opcode & ~0xF) === 0x70 || (encoding.opcode & ~0xF) === 0x0F80);
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const condition_index = encoding.opcode & 0xF;
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body.push(`analysis.ty = ::analysis::AnalysisType::Jump { offset: jump_offset as i32, condition: Some(${condition_index}), is_32: cpu.osize_32() };`);
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}
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else
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{
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body.push(`analysis.ty = ::analysis::AnalysisType::Jump { offset: jump_offset as i32, condition: None, is_32: cpu.osize_32() };`);
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}
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}
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else
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{
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body.push(imm_read + ";");
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}
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}
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if(encoding.extra_imm16)
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{
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console.assert(imm_read);
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body.push(gen_call("cpu.read_imm16"));
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}
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else if(encoding.extra_imm8)
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{
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console.assert(imm_read);
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body.push(gen_call("cpu.read_imm8"));
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}
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return [].concat(
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body,
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instruction_postfix
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);
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}
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}
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function gen_table()
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{
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let by_opcode = Object.create(null);
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let by_opcode0f = Object.create(null);
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for(let o of x86_table)
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{
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let opcode = o.opcode;
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if((opcode & 0xFF00) === 0x0F00)
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{
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opcode &= 0xFF;
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by_opcode0f[opcode] = by_opcode0f[opcode] || [];
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by_opcode0f[opcode].push(o);
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}
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else
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{
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opcode &= 0xFF;
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by_opcode[opcode] = by_opcode[opcode] || [];
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by_opcode[opcode].push(o);
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}
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}
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let cases = [];
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for(let opcode = 0; opcode < 0x100; opcode++)
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{
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let encoding = by_opcode[opcode];
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console.assert(encoding && encoding.length);
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let opcode_hex = hex(opcode, 2);
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let opcode_high_hex = hex(opcode | 0x100, 2);
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if(encoding[0].os)
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{
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cases.push({
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conditions: [`0x${opcode_hex}`],
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body: gen_instruction_body(encoding, 16),
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});
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cases.push({
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conditions: [`0x${opcode_high_hex}`],
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body: gen_instruction_body(encoding, 32),
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});
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}
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else
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{
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cases.push({
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conditions: [`0x${opcode_hex}`, `0x${opcode_high_hex}`],
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body: gen_instruction_body(encoding, undefined),
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});
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}
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}
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const table = {
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type: "switch",
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condition: "opcode",
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cases,
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default_case: {
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body: ["dbg_assert!(false);"]
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},
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};
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if(to_generate.analyzer)
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{
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const code = [
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"#[cfg_attr(rustfmt, rustfmt_skip)]",
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"pub fn analyzer(opcode: u32, cpu: &mut ::cpu_context::CpuContext, analysis: &mut ::analysis::Analysis) {",
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table,
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"}",
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];
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finalize_table_rust(
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OUT_DIR,
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"analyzer.rs",
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rust_ast.print_syntax_tree([].concat(code)).join("\n") + "\n"
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);
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}
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const cases0f_16 = [];
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const cases0f_32 = [];
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for(let opcode = 0; opcode < 0x100; opcode++)
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{
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let encoding = by_opcode0f[opcode];
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console.assert(encoding && encoding.length);
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let opcode_hex = hex(opcode, 2);
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if(encoding[0].os)
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{
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cases0f_16.push({
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conditions: [`0x${opcode_hex}`],
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body: gen_instruction_body(encoding, 16),
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});
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cases0f_32.push({
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conditions: [`0x${opcode_hex}`],
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body: gen_instruction_body(encoding, 32),
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});
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}
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else
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{
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let block = {
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conditions: [`0x${opcode_hex}`],
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body: gen_instruction_body(encoding, undefined),
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};
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cases0f_16.push(block);
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cases0f_32.push(block);
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}
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}
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const table0f_16 = {
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type: "switch",
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condition: "opcode",
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cases: cases0f_16,
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default_case: {
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body: ["dbg_assert!(false);"]
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},
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};
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const table0f_32 = {
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type: "switch",
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condition: "opcode",
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cases: cases0f_32,
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default_case: {
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body: ["dbg_assert!(false);"]
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},
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};
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|
|
if(to_generate.analyzer0f_16)
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{
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const code = [
|
|
"#![allow(unused)]",
|
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"#[cfg_attr(rustfmt, rustfmt_skip)]",
|
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"pub fn analyzer(opcode: u8, cpu: &mut ::cpu_context::CpuContext, analysis: &mut ::analysis::Analysis) {",
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table0f_16,
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"}"
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];
|
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|
|
finalize_table_rust(
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|
OUT_DIR,
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|
"analyzer0f_16.rs",
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|
rust_ast.print_syntax_tree([].concat(code)).join("\n") + "\n"
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|
);
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|
}
|
|
|
|
if(to_generate.analyzer0f_32)
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|
{
|
|
const code = [
|
|
"#![allow(unused)]",
|
|
"#[cfg_attr(rustfmt, rustfmt_skip)]",
|
|
"pub fn analyzer(opcode: u8, cpu: &mut ::cpu_context::CpuContext, analysis: &mut ::analysis::Analysis) {",
|
|
table0f_32,
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|
"}"
|
|
];
|
|
|
|
finalize_table_rust(
|
|
OUT_DIR,
|
|
"analyzer0f_32.rs",
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|
rust_ast.print_syntax_tree([].concat(code)).join("\n") + "\n"
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|
);
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|
}
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|
}
|