Commit graph

72 commits

Author SHA1 Message Date
Fabian 93ffd50969 Custom codegen for more sse move aliases (660F29/660F6F/F30F7F) 2020-08-30 19:37:15 -05:00
Fabian 75e5c2a56f Codegen for 8-bit shifts (D0/D2) 2020-08-30 19:37:15 -05:00
Fabian 815e5d338e Codegen more fpu instructions and run their tests (D9_6, DA_5) 2020-08-30 19:37:15 -05:00
Fabian fdd1dc377d Custom codegen for xadd (0FC1) 2020-08-30 19:37:15 -05:00
Fabian 874818866a Codegen for mul32 + custom mul/imul (F7_[45]) 2020-08-30 19:37:15 -05:00
Fabian 2a3e4bfa86 Minor: Remove unused 2020-08-30 19:37:15 -05:00
Fabian 7024207fa4 Codegen for inc/dec (group 40-4F) 2020-08-30 19:37:15 -05:00
Fabian a8308b988d Store registers in locals
This changes registers to be temporarily stored in wasm locals, across
each complete wasm module. Registers are moved from memory to locals
upon entering the wasm module and moved from locals to memory upon
leaving. Additionally, calls to functions that modify registers are
wrapped between moving registers to memory before and moving back to
locals after. This affects:

1. All non-custom instructions
2. safe_{read,write}_slow, since it may page fault (the slow path of all memory accesses)
3. task_switch_test* and trigger_ud
4. All block boundaries
5. The fallback functions of gen_safe_read_write (read-modify-write memory accesses)

The performance benefits are currently mostly eaten up by 1. and 4. (if
one calculates the total number of read/writes to registers in memory,
they are higher after this patch, as each instructions of typ 1. or 4.
requires moving all 8 register twice). This can be improved later by the
relatively mechanical work of making instructions custom (not
necessarily full code generation, only the part of the instruction where
registers are accessed). Multi-page wasm module generation will
significantly reduce the number of type 4. instructions.

Due to 2., the overall code size has significantly increased. This case
(the slow path of memory access) is often generated but rarely executed.
These moves can be removed in a later patch by a different scheme for
safe_{read,write}_slow, which has been left out of this patch for
simplicity of reviewing.

This also simplifies our code generation for storing registers, as

    instructions_body.const_i32(register_offset);
    // some computations ...
    instruction_body.store_i32();

turns into:

    // some computations ...
    write_register(register_index);

I.e., a prefix is not necessary anymore as locals are indexed directly.

Further patches will allow getting rid of some temporary locals, as
registers now can be used directly.
2020-08-30 19:37:15 -05:00
Fabian ed5ecda0ae Custom implementation for pop [mem] (preparation for registers-in-locals) 2020-08-30 19:37:15 -05:00
Fabian 730919e317 Use gen_trigger_ud for invalid LEA encodings 2020-08-30 19:37:15 -05:00
Fabian f5540d9edf Use pop16_reg_jit for pop esp 2020-08-30 19:37:15 -05:00
Fabian 32f988a08d Pass JitContext to gen_get_reg* (preparation for registers-in-locals) 2020-08-30 19:37:15 -05:00
Fabian 0c42ea0d1f Custom code generation for leave (C9) 2020-08-30 19:37:15 -05:00
Fabian 837e6ff362 Custom code generation for ret imm (C2) 2020-08-30 19:37:15 -05:00
Fabian c0f1d2a487 Custom code generation for arith al/ax/eax, imm (group [0123][45CD], A8/A9) 2020-08-30 19:37:15 -05:00
Fabian f14e9528d6 Custom code generation for cmovcc (0F40-0F4F) 2020-08-30 19:37:15 -05:00
Fabian aef22e38ad Add missing tracking of jit exit points 2020-08-30 19:37:15 -05:00
Fabian 69b834c8de Move condition function generation into codegen module and use it for cmovcc/setcc 2020-08-30 19:37:15 -05:00
Fabian c9163c2df5 Custom code generation for mov reg, imm (B0-BF) 2020-08-30 19:37:15 -05:00
Fabian 2837ccd06b Support for gen_safe_read128 and code generation for MOVDQU (F30F6F) 2020-08-30 19:37:15 -05:00
Fabian dca6be2d94 Also generate nop for prefetch instruction 2020-08-30 19:37:15 -05:00
Fabian 440b67eda5 Support for gen_safe_write128 and code generation for MOVAPS/MOVDQA (0F29/660F7F) 2020-08-30 19:37:15 -05:00
Fabian e2ab5eabdd Code generation for missing memory operations (8-bit shifts, shrd, shld, xadd) 2020-08-30 19:37:15 -05:00
Fabian ec846b34d9 Codegen for fpu instructions (misc instructions) (D9_[14], DB_5, DD_5, DF_4) 2020-08-30 19:37:15 -05:00
Fabian 1eab44746b Codegen for fpu instructions (fldcw/fstcw) (D9_5, D9_7) 2020-08-30 19:37:15 -05:00
Fabian fdce557820 Codegen for fpu instructions (memory stores: fst/fstp/fist/fistp) (D9_[23], DB_[23], DD_[23], DF_[237]) 2020-08-30 19:37:15 -05:00
Fabian 7c99bdae74 Codegen for fpu instructions (memory loads: fld, fild) (D9_0, DB_0, DD_0, DF_5) 2020-08-30 19:37:15 -05:00
Fabian c452c357dd Codegen for fpu instructions (DE group) 2020-08-30 19:37:15 -05:00
Fabian 21caefbffd Codegen for fpu instructions (DC group) 2020-08-30 19:37:15 -05:00
Fabian f6718c3ead Fix a few missing local frees 2020-08-30 19:37:15 -05:00
Fabian ec059a9f27 Codegen for fpu instructions (D8 group) 2020-08-30 19:37:15 -05:00
Fabian 7e3f1ad401 gen_fn: Accept wasm builder, not jit context 2020-08-30 19:29:54 -05:00
Fabian 5eaece7743 jit memory moves with immediate address (A0/A1/A2/A3) 2020-08-30 19:29:54 -05:00
Fabian 8de547455e jit memory access for imul 2020-08-30 19:29:54 -05:00
Fabian 6a2cd6419d jit memory access for 8-bit read-modify-write operations with immediate 2020-08-30 19:29:54 -05:00
Fabian 2635ed71b4 jit memory access for 8-bit read-modify-write operations 2020-08-30 19:29:54 -05:00
Fabian d37c8295aa jit: Mask shifts and rotates to 5 bits 2020-08-30 19:29:54 -05:00
Awal Garg 54151e2306 jit 0x0FBF 2020-08-30 19:29:54 -05:00
Awal Garg 0377e95c42 jit 0x0FB7 2020-08-30 19:29:54 -05:00
Fabian 41b60d278c Accept builder in gen_jmp_rel16, simplifying 2020-08-30 19:29:54 -05:00
Fabian 5dd26ead30 Generate code for memory instructions (0F4*, 0F9*, 0FAF: cmovcc, setcc, imul) 2020-08-30 19:29:54 -05:00
Fabian de01a4b265 Generate code for memory instructions (F6/F7/FF_{0,1}: test/inc/dec) 2020-08-30 19:29:54 -05:00
Fabian fa50294b47 Generate code for read-modify-write instructions (C1/D1/D3: Shifts and rotates) 2020-08-30 19:29:54 -05:00
Fabian 3706bcac12 Use jit for read-modify-write arithmetic instructions 2020-08-30 19:29:54 -05:00
Fabian cfb9cd8abe Partial custom implementation for arithmethic instructions with read-memory 2020-08-30 19:29:54 -05:00
Fabian 9de2b926a7 Custom implementations for test instruction (only wrapper) 2020-08-30 19:29:54 -05:00
Fabian 9164e0a48f Custom implementation for 'mov r/m, imm' 2020-08-30 19:29:54 -05:00
Fabian 1d24c5952d Cleanup of codegen api 2020-08-30 19:29:54 -05:00
Fabian b0eff6b951 Implement 8-bit memory accesses 2020-08-30 19:29:54 -05:00
Fabian d4d7d236d5 Make all instructions non-faulting; handle faulting case in gen_safe_{read,write} (#44) 2020-08-30 19:29:54 -05:00