Commit graph

296 commits

Author SHA1 Message Date
Fabian b0eff6b951 Implement 8-bit memory accesses 2020-08-30 19:29:54 -05:00
Fabian c36a179a5e Remove block_boundary from push 2020-08-30 19:29:53 -05:00
Fabian a5cbf53da5 Fix jit in presence of new page fault handling
Makes the following a block boundary:

- push
- Any non-custom instruction that uses modrm encoding
- Any sse/fpu instruction

This commit affects performance negatively. In order to fix this, the
above instructions need to be implemented using custom code generators
for the memory access.
2020-08-30 19:29:53 -05:00
Fabian a88420910d Handle pagefaults without JS exceptions
This commit makes the return type of most basic memory access primitives
Result, where the Err(()) case means a page fault happened, the
instruction should be aborted and execution should continue at the page
fault handler.

The following primites have a Result return type: safe_{read,write}*,
translate_address_*, read_imm*, writable_or_pagefault, get_phys_eip,
modrm_resolve, push*, pop*.

Any instruction needs to handle the page fault cases and abort
execution appropriately. The return_on_pagefault! macro has been
provided to get the same behaviour as the previously used JS exceptions
(local to the function).

Calls from JavaScript abort on a pagefault, except for
writable_or_pagefault, which returns a boolean. JS needs to check
before calling any function that may pagefault.

This commit does not yet pervasively apply return_on_pagefault!, this
will be added in the next commit.

Jitted code does not yet properly handle the new form of page faults,
this will be added in a later commit.
2020-08-30 19:29:53 -05:00
Fabian 33acb48fb9 Implement cvtsd2si (#57) 2020-08-30 19:29:53 -05:00
Fabian 6fa702c8aa Implement {min,max,div}{p,s}{s,d} sse instructions (#57) 2020-08-30 19:29:53 -05:00
Fabian c10bbca85e Add sqrt{p,s}{d,s} instructions (#57) 2020-08-30 19:29:53 -05:00
Fabian 70ae4b720a Remove use of raising cpu exceptions for trigger_ud 2020-08-30 19:29:53 -05:00
Fabian 7e574dde52 Implement some floating point sse1/sse2 instructions (#57) 2020-08-30 19:29:53 -05:00
Fabian 9f2c78efb4 Add missing sse3 instruction and add note on others 2020-08-30 19:29:53 -05:00
Fabian 49961ade7c Remove hintable nops that were refitted for mpx instructions 2020-08-30 19:29:53 -05:00
Fabian e0aabb2937 Mark hintable nops as non-faulting 2020-08-30 19:29:53 -05:00
Fabian bdef74eced Generate code for task_switch_test{,_mmx}, use non-raising exceptions 2020-08-30 19:29:53 -05:00
Fabian 02a7bbb8f7 Implement hintable nops 2020-08-30 19:29:53 -05:00
Fabian f43ab3387a Remove use of cpu exceptions for trigger_gp for instructions 2020-08-30 19:29:53 -05:00
Fabian 5e82bc0e00 Remove use of cpu exceptions for trigger_ss (partially including switch_seg) 2020-08-30 19:29:53 -05:00
Fabian 4ee7da8f83 Remove use of cpu exceptions for divisions 2020-08-30 19:29:53 -05:00
Awal Garg b3e415cf9f jit inline 0xC3 2020-08-30 19:29:53 -05:00
Awal Garg c2c5e4f35c jit inline 0xC7
The generated rust code doesn't call read_imm* functions for custom
instructions now for the memory variant branches when both immediate
values and modrm byte is used
2020-08-30 19:29:53 -05:00
Awal Garg 4d622c165e jit inline nop instructions 2020-08-30 19:29:53 -05:00
Fabian 1253b72906 Generate prefix handling for string instructions 2020-08-30 19:29:13 -05:00
Fabian 3a8d644d75 Port jit to Rust
The following files and functions were ported:
- jit.c
- codegen.c
- _jit functions in instructions*.c and misc_instr.c
- generate_{analyzer,jit}.js (produces Rust code)
- jit_* from cpu.c

And the following data structures:
- hot_code_addresses
- wasm_table_index_free_list
- entry_points
- jit_cache_array
- page_first_jit_cache_entry

Other miscellaneous changes:
- Page is an abstract type
- Addresses, locals and bitflags are unsigned
- Make the number of entry points a growable type
- Avoid use of global state wherever possible
- Delete string packing
- Make CachedStateFlags abstract
- Make AnalysisType product type
- Make BasicBlockType product type
- Restore opcode assertion
- Set opt-level=2 in debug mode (for test performance)
- Delete JIT_ALWAYS instrumentation (now possible via api)
- Refactor generate_analyzer.js
- Refactor generate_jit.js
2020-08-30 19:29:13 -05:00
Fabian 9b2b3250df Fix 8-bit jumps in 16-bit mode 2020-08-30 19:27:07 -05:00
Fabian 5995414f87 JIT: Follow call instructions 2020-08-30 19:27:07 -05:00
Fabian ad7fa728b5 Annotate some instructions 2020-08-30 19:27:07 -05:00
Fabian 8466ca205e Mark ud2 instruction as block boundary 2020-08-30 19:27:07 -05:00
Fabian cba5491fc4 Multiple jit block entry points
- introduce multiple entry points per compiled wasm module, by passing
  the initial state to the generated function.
- continue analysing and compiling after instructions that change eip, but
  will eventually return to the next instruction, in particular CALLs
  (and generate an entry point for the following instruction)

This commit is incomplete in the sense that the container will crash
after some time of execution, as wasm table indices are never freed
2020-08-30 19:27:02 -05:00
Amaan Cheval 2128f07796 jit: Inline 0x89 and 0x8b opcodes's reg variants 2020-07-21 20:10:14 -05:00
Fabian 39d8d17031 Make 8f custom, simplify generate_jit by removing handling of requires_prefix_call 2020-07-21 20:10:14 -05:00
Fabian ded423b1c5 x86 table: Add remaining 0f instructions, simplify gen scripts 2020-07-21 20:10:14 -05:00
Fabian a9b5f153a8 Move around and add some assertions 2020-07-21 20:10:14 -05:00
Fabian f8349af093 New block analysis, generation of state machine with multiple basic blocks
This commit consists of three components:

1. A new generated x86-parser that analyses instructions. For now, it
   only detects the control flow of an instruction: Whether it is a
   (conditional) jump, a normal instruction or a basic block boundary
2. A new function, jit_find_basic_blocks, that finds and connects basic
   blocks using 1. It loosely finds all basic blocks making up a function,
   i.e. it doesn't follow call or return instructions (but it does follow
   all near jumps). Different from our previous analysis, it also finds
   basic blocks in the strict sense that no basic block contains a jump
   into the middle of another basic block
3. A new code-generating function, jit_generate, that takes the output
   of 2 as input. It generates a state machine:
   - Each basic block becomes a case block in a switch-table
   - Each basic block ends with setting a state variable for the following basic block
   - The switch-table is inside a while(true) loop, which is terminated
     by return statements in basic blocks which are leaves

Additionally:
- Block linking has been removed as it is (mostly) obsoleted by these
  changes. It may later be reactived for call instructions
- The code generator API has been extended to generate the code for the state machine
- The iterations of the state machine are limited in order to avoid
  infinite loops that can't be interrupted
2020-07-21 20:10:14 -05:00
Fabian 0d5ca58354 Minor: Use freeze on instruction objects 2020-07-21 20:10:14 -05:00
Amaan Cheval 41c8241d5e x86_table: Mark state-altering instructions as JIT block boundaries
These instructions, if included within a compiled JIT block, may alter the
state_flags of a block entry (such as whether flat segmentation is used or not),
which may invalidate the block that is running - this caused bugs in OpenBSD
because of a block like this being compiled:

0xF81F2: 8E DB                mov ds, bx
0xF81F4: 8E D3                mov ss, bx
0xF81F6: 66 8B 26 B8 F5       mov esp, dword ptr [0xf5b8] <--
0xF81FB: 66 89 36 B8 F5       mov dword ptr [0xf5b8], esi <--

The memory accesses implicitly use DS. If we include flat-segmenetation as a
flag within state_flags and optimize calls to get_seg based on it, this behavior
would cause issues (and did, in OpenBSD).

By marking these instructions as block boundaries, we remediate that issue.
2020-07-21 20:10:14 -05:00
Amaan Cheval 4d87bebee9 gen: s/jump/block_boundary/ 2020-07-21 20:10:14 -05:00
Amaan Cheval 1f0e7c3ce0 fpu: Have opcode 0xDF use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval fca80793b8 fpu: Have opcode 0xDE use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval 4910777084 fpu: Have opcode 0xDD use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval 33c2b72553 fpu: Have opcode 0xDC use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval c3a856e944 fpu: Have opcode 0xDB use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval 0f23cf2745 fpu: Have opcode 0xDA use fixed_g instruction functions 2020-07-21 20:10:14 -05:00
Amaan Cheval df86637cb8 fpu: Have opcode 0xD9 use fixed_g 2020-07-21 20:10:14 -05:00
Amaan Cheval 173be47658 fpu: Have opcode 0xD8 use fixed_g and the regular instruction decoder 2020-07-21 20:10:14 -05:00
Awal Garg 54a43ab437 improve segment prefix handling and custom code generation for lea 2020-07-21 20:10:14 -05:00
Amaan Cheval 843527ac04 Apply stack_size_32 cache optimization to push r/m 2020-07-21 20:10:14 -05:00
Amaan Cheval 3ffb2ac35f Apply stack_size_32 cache optimization to push imm 2020-07-21 20:10:14 -05:00
Amaan Cheval 3512d34314 Optimize push/pop JIT instructions to not check stack_size_32
We generate a version of the push/pop instruction with the stack_size_32 fixed,
since the state tends not to change much. If it does change, state_flags won't
match the output of pack_current_state_flags and the cache entry will therefore
be invalidated.
2020-07-21 20:10:14 -05:00
Fabian f5938caa5a Link blocks for conditional jumps 2020-07-21 20:10:14 -05:00
Amaan Cheval bbe7d3d1d1 Add nonfaulting property to instructions in x86_table
See:
https://gist.github.com/AmaanC/faff7066d16f1dee4bbbd6b73a72d831

From the geek32[1] sheet, the criteria for nonfaulting instructions used was:

```
groups = ['arith', 'logical', 'conver', 'datamov', 'datamov arith', 'shftrot', 'flgctrl'];

// Excluded because they may trigger faults, so the optimization can't apply to them
excluded_opcodes = [
    // May trigger_ud
    '0x8C',
    // switch_seg may fault
    '0x8E',
    // mov to/from seg:offset (memory accesses)
    '0xA0',
    '0xA1',
    '0xA2',
    '0xA3',
    // Unimplemented in v86
    '0xD50A',
    '0x0F38F0',
    '0x0F38F1',
];
// Keywords that indicate a group/instruction which may fault
excluded_row_words = ['fpu', 'simd', 'mmx', 'sse', 'vmx', 'XLAT', 'DIV', 'AMX', 'AAM', 'CLI', 'STI', 'CMPXCHG8B'];
```

[1] http://ref.x86asm.net/geek32.html#x0F90
2020-07-21 20:10:14 -05:00
Fabian f53aba84b5 Linking compiled blocks 2020-07-21 20:10:13 -05:00
Fabian cf687afe37 Mark hlt as changing eip
Not strictly necessary, as it escapes execution using
MAGIC_CPU_EXCEPTION, but a good idea in case it changes later
2020-07-21 20:10:13 -05:00
Fabian 0b32b05deb Address review 2020-07-21 20:10:13 -05:00
Fabian 96c6da294c Fix popf handling for jit 2020-07-21 20:10:13 -05:00
Fabian 815c7a33bf Fix STI handling for jit 2020-07-21 20:10:13 -05:00
Fabian e19e71386b Revert "Replace prefix_call with custom_resolve_modrm"
This reverts commit c7c42065ac4e8cdc2f8653b36a32d1df9cb26a2e.
2020-07-21 20:10:13 -05:00
Fabian 96ad9f80a1 Annotate instruction table with jumping instructions 2020-07-21 20:10:13 -05:00
Amaan Cheval b3a4a30a9f Implement pandnp{s,d}, xmm/m128 2020-07-21 20:10:13 -05:00
Amaan Cheval 91c6e08864 Implement orp{s,d}, xmm/m128 2020-07-21 20:10:13 -05:00
Amaan Cheval 70749c6aff Minor: Update comment for maskmovq and maskmovdqu 2020-07-21 20:10:12 -05:00
Amaan Cheval e4b3032266 Implement paddd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval bb58b8be45 Implement paddw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval d109faefb8 Implement paddb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 6d84b62bc0 Implement psubq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 0100369eaf Implement psubq mm, mm/m64 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 4949ffddd2 Implement psubw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval e8cf6ebdc3 Implement psubb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval e7abcdae8c Update maskmovdqu's entry in x86 encoding table 2020-07-21 20:10:12 -05:00
Amaan Cheval 6d609d2b42 Implement maskmovq mm, mm 2020-07-21 20:10:12 -05:00
Amaan Cheval c2801e6ef8 Implement psadbw xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 2f949ef93f Implement psadbw mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval 7b34662717 Implement pmaddwd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval b33c136a25 Implement pmuludq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval cfe26d5e33 Implement pmuludq mm, mm/m64 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 2ccf7fbb93 Implement pslld xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval d002913329 Implement psllw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 9b9c73a706 Implement pmaxsw xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 52b43b00bc Implement pmaxsw mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval ccd57dfcd0 Implement paddsw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval e71be08f7a Implement paddsb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 96ad95fcd8 Implement pminsw xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 08158d69e2 Implement pminsw mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval 69001dbd8a Implement psubsw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval df20bd5742 Implement psubsb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval a4029538f6 Implement movntq m64, mm 2020-07-21 20:10:12 -05:00
Amaan Cheval ef289aab7a Implement pmulhw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 91b0b9a41e Implement pmulhuw mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval 5a26ae8bb0 Implement pavgw xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval da697b72c2 Implement pavgw mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval de2e118f91 Implement psrad xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 33adb1a7f6 Implement psraw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 58fe73f3de Implement pavgb xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 16c0f9ce5e Implement pavgb mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval c025717e46 Implement pandn xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 41fac79092 Implement pmaxub mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval 4218f36b13 Implement pand xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 61f6c96717 Implement pminub mm, mm/m64 2020-07-21 20:10:12 -05:00
Amaan Cheval d7259a5d13 Implement psubusw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 6e147c048c Implement psubusb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 9de9e9da00 Implement pmovmskb r, mm 2020-07-21 20:10:12 -05:00
Amaan Cheval 5cde440520 Implement movdq2q mm, xmm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval dc49fcaf6d Implement movq2dq xmm, mm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 5686eccfd6 Implement paddq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 538d8b6293 Implement paddq mm, mm/m64 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 6dabca0139 Implement psrld xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval f80903ae77 Implement psrlw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 08f9667de4 Implement pextrw r32, mm, imm8 2020-07-21 20:10:12 -05:00
Amaan Cheval daaa9c9533 Implement pinsrw xmm, r32/m16, imm8 2020-07-21 20:10:12 -05:00
Amaan Cheval 4f6bb4aaa1 Implement pinsrw mm, r32/m16, imm8 2020-07-21 20:10:12 -05:00
Amaan Cheval b4a453c80c Implement pslldq xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 5d7b6029e5 Implement psllq xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval ad26b2cac5 Implement psrldq xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 81fe37f21d Implement pslld xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 948fd01cb5 Implement psrad xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 24d88a60e9 Implement psrld xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 2540282ccc Implement psllw xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval e03ada1e86 Implement psraw xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval b0d3b57121 Implement psrlw xmm, imm8 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 4a43dd3b40 Implement punpckhqdq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 5dc340bf4f Implement punpcklqdq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval d0802a077a Implement packssdw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval e0f3a0a591 Implement punpckhdq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval a1fae817ca Implement punpckhwd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 9d205a6838 Implement pcmpgtd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 75499a52c1 Implement pcmpgtw xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 22ca7d5388 Implement pcmpgtb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval a36eed440a Implement packsswb xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 28ce2f26cb Implement punpckldq xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 58e9bd803f Implement movmskpd r, xmm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 2394b9fe65 Implement movmskps r, xmm 2020-07-21 20:10:12 -05:00
Amaan Cheval 430743f535 Implement movhpd m64, xmm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 3e65d5a3d8 Implement movhps m64, xmm 2020-07-21 20:10:12 -05:00
Amaan Cheval ced2e67889 Implement movhpd xmm, m64 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval da94185d2e Implement movhps xmm, m64 and movlhps xmm, xmm (shared opcode) 2020-07-21 20:10:12 -05:00
Amaan Cheval 694434fb7b Implement unpckhpd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval c33b3336e6 Implement unpckhps xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 3ef90091ed Implement unpcklps xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Amaan Cheval 909ffd35ef Implement movsd xmm/m64, xmm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 9cc948ceac Implement movupd xmm/m128, xmm (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 7e9c94d5d5 Implement movsd xmm, xmm/m64 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 11342ed828 Implement movupd xmm, xmm/m128 (sse2) 2020-07-21 20:10:12 -05:00
Amaan Cheval 8257fcac53 Implement movlps xmm, m64 and movhlps xmm, xmm (shared opcode) 2020-07-21 20:10:12 -05:00
Amaan Cheval 0f2dba4cc8 Implement movss xmm/m32, xmm 2020-07-21 20:10:12 -05:00
Amaan Cheval 58bfd4593c Implement movups xmm/m128, xmm 2020-07-21 20:10:12 -05:00
Amaan Cheval 7013405402 Implement movss xmm, xmm/m32 2020-07-21 20:10:12 -05:00
Amaan Cheval 662c3fb2d2 Implement movups xmm, xmm/m128 2020-07-21 20:10:12 -05:00
Fabian 975a06269e Squash
2e469796 Minor
fab422ef Improve generation of 0f instructions
08ad7fe9 Improved if-else generation
3f81014d Minor: Align test output
4a3a84ef Generate modrm tests
61aa1875 Simplify
a6e47954 Generate decoding of immediate operands
435b2c10 Fix warnings
e4933042 Add missing immediate operand
3f3810c7 Generate immediate operands for instructions with modrm byte
a0aa7b1f Make memory layout in nasm tests clearer
6b8ef212 Remove 'g' property from instruction table (implied by 'e')
bf15c58c Remove unused declarations
1e543035 Remove useless `| 0` and `>>> 0` javascriptisms
1ccc5d53 Fix headers
8b40c532 Update qemu tests with changes from qemu
ec9b0fb5 Port xchg instructions to C
c73613e7 Port virt_boundary_* to C
d61d1241 Add headers
fd19f22c Make written value in write8 and write16 int32_t
497dcaec Generate read_imm for instructions with a modrm byte
8b7003d6 Generate read_imm8s
0cc75498 Remove read_op
9d716086 Trigger unimplemented_sse for partial sse instructions with prefix
8d5edd03 Remove unimplmented sse c-to-js hack
585d3565 Remove | 0
308124b2 Use int32_t as return value
f193f8e1 Use JS version of cvttsd2si for now
12747b97 Generate trigger_ud for missing modrm branches
770f674e Split 0f00 and 0f01 into multiple instructions depending on modrm bits
1cb372a3 Generate decoder for some 0f-prefix instructions
cec7bc63 Disable unused parameter warnings in instruction functions
807665b1 Generate read_imm for 0f/jmpcc
cdf6eccc Generate modrm decoding for shld
04528429 Create temporary files in /tmp/, not cwd
d8f3fbd8 Generate modrm/imm decoding for shld
00ef0942 Generate modrm decoding for bts
f531984b Generate modrm decoding for shrd and imul
07569c53 Generate modrm decoding cmpxchg
535ff190 Generate modrm decoding for lfs/lgs/lss
2f8ced8d Generate modrm decoding for btr and btc
95de6c66 Generate modrm decoding for movzx
c4d07e7e Generate modrm decoding for bsf and bsr
f0985d26 Generate modrm decoding for movsx
4b30937a Generate modrm decoding for xadd
a422eb27 Generate modrm decoding for movnti
e5501d3c Generate modrm decoding for mov to/from control/debug registers
bce11ec5 Generate modrm decoding for lar/lsl
5729a23c Fix access to DR4 and DR5 when cr4.DE is clear
44269a81 Specify immediate size explicitly instead of inferring it
82b2867a Fix STR instruction
98a9cc89 Log failing assertion
6d2f9964 Fix rdtsc
00260694 Log GP exceptions
7916883d Port trigger_ud and trigger_nm to C
36fedae9 Remove unused code
e08fabd0 Generate modrm decoding for 0f00 and 0f01
8ae8174d Generate modrm decoding for 0fae and 0fc7 (fxsave, cmpxchg8, etc.)
26168164 Generate modrm+immediate decoding for 0fba (bit test with immediate operand)
6adf7fa7 Simplify create_tests.js (unused prefix call)
c77cbdd8 Add comments about the implementation of pop [addr]
4640b4fe Simplify prefix call
a81a5497 Don't use var
3ca5d13d Separate call name and arguments in code generator
3191a543 Simplify other prefix call (8D/lea)
5185080e Update generated code (stylistic changes and #ud generation)
93b51d41 Remove unused wasm externals
e4af0a7f Avoid hardcoding special cases in code generator (lea, pop r/m)
654a2b49 Avoid hardcoding special cases in code generator (enter/jumpf/callf)
fd1a1e86 Commit generated code (only stylistic changes)
7310fd1a Simplify code generator by merging code for with and without 0f prefix
e7eae4af Simplify code generator by merging code for immediate operands
00fafd8a Improve assertions
db084e49 Simplify code generator (modrm if-else)
0a0e4c9e Improve code generation of switch-case
ce292795 Clarify some comments
37cf33fa Generate code in if/else blocks
cbcc33fc Document naming scheme
e30b97eb Generate modrm decoding for 0f12 (sse) instruction
24b72c2f movlpd cannot be used for register-to-register moves
72d72995 Generate modrm decoding for 0f13 (sse) instruction and disable register-to-register moving
75d76fbb Generate modrm decoding for 0f14 (sse) instruction
ac8965a7 Generate modrm decoding for 0f28-0f2b (movap, movntp)
e919d33e Generate modrm decoding for cvttsd2si
5f2ca2b4 Generate modrm decoding for andp and xorp
c8d1c6de Generate modrm decoding for 0f60-0f70 (sse instructions)
ae4ed46d Add multi-byte nop and prefetch to nasm test, generate modrm decoding
718a1acf Print qemu test error message more useful
d1ecc37e Generate modrm decoding for 0f70-0f80 (sse instructions)
6a7219a5 Generate modrm decoding for popcnt
25278217 Generate modrm decoding for 0f71-0f73 (sse shift with immediate byte)
ed1ec81b Generate modrm decoding for the remaining sse instructions (0fc0-0fff)
42bc5a6f Use 64-bit multiplication for native code
dda3fb39 Remove old modrm-decoding functions
717975ef Move register access functions to cpu.c
aee8138f Remove read_op, read_sib, read_op0F, read_disp
f31317f2 Rename xmm/mmx register access functions
a525e70b Remove 32-bit access to reg_xmm and reg_mmx
c803eabc Rename s8/s16/s32 to i8/i16/i32
9fbd2ddf Don't use uninitialised structs
942eb4f7 Use 64-bit load for mmx registers and assert reg64 and reg128 size
f94ec612 Use 64-bit writes for write_xmm64
08022de9 Use more efficient method for some 128-bit stores
9d5b084c Make timestamp counter unsigned
2ef388b3 Pass 64-bit value to safe_write64
4cb2b1be Optimise safe_write64 and safe_write128
b0ab09fb Implement psllq (660ff3)
9935e5d4 Optimise safe_read64s and safe_read128s
af9ea1cc Log cl in cpuid only if relevant
be5fe23e Add multi-op cache (disabled by default through ENABLE_JIT macro) and JIT paging test (similar to QEMU test).
aa2f286e Don't initialise group_dirtiness with 1 as it increases the binary size significantly
b8e14ed9 Remove unused reg_xmm32s
bc726e03 Implement dbg_log for native code with format characters 'd' and 'x'
454039d6 Fix store task register
63a4b349 Remove unnecessary parens and clean up some log statements
4cc96814 Add logop and dbg_trace imports
7940655d Only inhibit interrupts if the interrupt flag was 0 in STI
876c68a7 Split create_tests into create_tests and generate_interpreter
aa82499f Move detection of string instructions to x86_table
f3840ec2 Move C ast to separate file
90400703 Skip tests for lfence/mfence/sfence, clarify their encoding
4a9d8204 elf: Hide log messages when log level is zero
a601c526 Allow setting log level via settings
8a624453 Add cpu_exception_hook to debug builds
f9e335bf Nasm: Test exceptions
599ad088 logop: Format instruction pointer as unsigned
f95cf22b Don't skip zero dividing tests
2a655a0e Remove get_seg_prefix_ds from read_moffs (preparation for calling read_moffs from the code generator)
bc580b71 Remove obsolete comment
e556cee0 Fix nasmtest dependencies in makefile and clean
dcb1e72b Use all cores on travis
86efa737 Replace all instances of u32 & 0xFFFF with the respective u16 accesses
98b9f439 Use u8 instead of bit-shifts and masks from u32
b43f6569 Replace all instances of u32 >> 16 with the respective u16 accesses
9bfa72c7 Remove unnecessary parens
9cf93734 Clean up remaining instance of u32 with a mask instead of u16
22d4117f Correct order of writes in virt_boundary_write32
6734c7c1 Fix keyboard on ios, fixes #105
858a4506 Add missing file, c_ast.js
1d62e39e Move instruction naming scheme into function
f4816852 Reorder some code
69d49788 Minor improvements
0493e05f Add util.js
af9000c1 Improve full test
e5feba31 Add missing export
c7c42065 Replace prefix_call with custom_resolve_modrm
3186e6ad Add support for "%%" format string to dbg_log_wasm for printf import
efe54fad Add barebones instrumentation profiler (disabled by default).
c9f0d462 Implement movlps m64, xmm and enable its test
42869a12 Add tests for cross-page reads/writes confirmed with byte reads/writes
d68976ea Mask word values in port byte reads
9758d51e Add PS2_LOG_VERBOSE
5f52f037 Update NASM Makefile to include all dependencies to prevent unnecessary recompilation
2c71f927 Have NASM test generator use a seedable PRNG to allow for faster incremental tests
e4aa45bb Add chunk{16,32}_rw paging tests; instructions that read and write to memory
bdf538a2 add codegen to cpu constructor
aa76ce8e add resolve_modrm16
14d7ecf1 refactor codegen
b710319f [rebased] Merge branch codegen
0565ea42 minor refactoring
071dff3f temporary fix for automatic cast warnings
57c504f2 fix modrm16 issue
c2db5d9e jit modrm32
85c04245 reinstate modrm_fn0 and modrm_fn1
be65dafd add ip and previous ip manipulating functions
ae00ef89 update codegen js interface
530a74fa squashed commit for refactor
2c692199 add codegen-test to build
c15afe68 prefix gen to codegen api
c9611533 codegen tests fixes
2020-07-21 20:10:12 -05:00